Principal/Lead Design Engineer – Memory Controller (CHI-G / DFI)

Canvendor; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Canvendor in San Jose, CA is seeking a Principal Design Engineer to lead RTL development for the Memory Controller subsystem, with CHI-G/DFI expertise. Onsite role, 12+ Months.

You will own microarchitecture updates, CHI-G/DFI interface logic, and collaborate with verification and design teams to meet timing and power targets.

Qualifications

• Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of RTL design experience in SystemVerilog/Verilog for SoC subsystems.
• Hands-on memory controller design (DDR4/DDR5/LPDDR) experience.
• Knowledge of ARM CHI/CHI-G protocol and coherency channels.
• Exposure to APB/AHB/AXI4/ACE interfaces.
• Experience with DFI and PHY-facing timing/command interfaces.
• Experience modifying large RTL codebases, not greenfield only.
• Synthesis, timing closure, and low-power design familiarity.
• Strong debugging with waveforms, formal tools, and lab equipment.

Responsibilities

• Modify and extend an existing memory controller RTL to support CHI-G and DFI changes.
• Own microarchitecture updates for command scheduling, arbitration, and QoS.
• Design CHI-G request/response/snoop channel logic for coherence.
• Develop DFI-compliant interface logic to PHY.
• Analyze timing/power/area impact and drive RTL through synthesis/STA.
• Collaborate with verification, DFT, and physical design teams for PPC targets.
• Debug pre/post-silicon memory controller issues related to timing and coherency.
• Produce updated microarchitecture specs and interface timing diagrams.
• Participate in design reviews and mentor junior engineers on CHI-G/DFI.

Skills

RTL design

SystemVerilog

Memory controller

CHI/CHI-G protocol

DFI interfaces

APB/AHB/AXI4

DFI timing

Synthesis & timing

Low-power design

Debugging with waveforms

Mentoring juniors

UVM verification

Education

Bachelor's/Master's in EE/CE

Tools

EDA tools

Simulation tools

Formal verification tools

Lab equipment

Job description

Job Title : Principal/Lead Design Engineer – Memory Controller (CHI-G / DFI)

Job Location : San Jose, CA(Onsite)

Duration : 12+Months

Job Description:

We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub Interface – Gateway) protocol and DDR/LPDDR/HBM PHY-facing DFI (DFI Interface). This role owns modifying and extending an existing memory controller design to accommodate new architectural requirements, protocol updates, and performance targets.

Key Responsibilities

• Modify and extend an existing memory controller RTL design to support new CHI-G protocol requirements and DFI interface changes
• Own microarchitecture updates for command scheduling, arbitration, QoS, and bank/rank management within the memory controller
• Design and integrate CHI-G request/response/snoop channel logic, ensuring protocol compliance and coherency correctness
• Develop and maintain DFI-compliant interface logic (command, write/read data, timing parameters) to PHY
• Analyze impact of new features on timing, power, and area; drive RTL changes through synthesis and STA closure
• Collaborate with verification, DFT, and physical design teams to ensure the modified design meets functional and PPA (Power, Performance, Area) goals
• Debug pre-silicon and post-silicon issues related to memory controller behavior, coherency, and interface timing
• Produce/update microarchitecture specs, interface timing diagrams, and design documentation reflecting the new changes
• Participate in design reviews and mentor junior engineers on CHI-G/DFI concepts

Required Qualifications

• Bachelor's/Master's in Electrical Engineering, Computer Engineering, or related field
• 8+ years of RTL design experience in SystemVerilog/Verilog for SoC subsystems
• Hands-on experience with memory controller design (DDR4/DDR5/LPDDR) or equivalent
• Working knowledge of ARM CHI/CHI-G protocol (coherency, request/response/snoop channels)
• Working knowledge of APB/AHB/AXI4/ACE interfaces
• Experience with the DFI specification and PHY-facing timing/command interfaces
• Experience modifying/extending existing large RTL codebases (not greenfield-only experience)
• Familiarity with synthesis, timing closure, and low-power design techniques
• Strong debugging skills using simulation waveforms, formal tools, and lab equipment

Preferred Qualifications

• Exposure to DFT, post-silicon bring-up, or PCB-level memory subsystem validation
• Familiarity with UVM-based verification flows (to collaborate effectively with verification teams)
• Experience with AI/LLM-assisted RTL development or design productivity tooling