Principal Engineer, CPU Architecture & Performance Research

Samsungsemiconductor; San Jose (CA); On-site; USD 219,000 - 351,000; Full time

Benefits offered by this job

401k

4+ weeks paid time off

Medical, dental, vision insurance

Charitable giving match

Emotional wellness support

Job summary

Samsung Semiconductor is seeking a Principal CPU Architecture & Performance Research Engineer in San Jose to lead the optimization of next-gen CPU microarchitectures. The role requires extensive experience in performance analysis and architectural design.

Candidates should have a Master's degree with over 18 years in the field or a PhD with 15+ years, along with strong expertise in CPU architectures. The position offers a competitive pay range of $219,000 – $351,000 USD plus comprehensive benefits.

Qualifications

• 18+ years of experience in Computer Engineering, Computer Science, or related field.
• 10+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC‑V, ARM, or X86 architectures.

Responsibilities

• Lead the definition, analysis, and optimization of CPU microarchitectures.
• Evaluate CPU micro‑architectural features for future cores.
• Drive performance analysis using simulators.

Skills

CPU microarchitecture

Performance engineering

C/C++ programming

Python programming

RISC-V architecture

Architectural simulators

Education

Master’s in Computer Engineering or related field with 18+ years experience

PhD with 15+ years experience

Tools

gem5

Job description

Principal, CPU Architecture & Performance Research Engineer

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 42918

What You’ll Do

Architecture Research Lab is seeking Principal CPU Architecture & Performance Engineer to lead the definition, analysis, and optimization of next‑generation CPU microarchitectures (RISC‑V core). This role is focused on end‑to‑end performance: from architectural trade‑offs and workload characterization to micro‑architectural modeling, simulation, and silicon bring‑up correlation. You will work closely with architecture, design, compiler, and system teams to drive performance and efficiency across a broad set of real‑world workloads.

• Define and evaluate CPU micro‑architectural features for future cores (frontend, execution engine, memory hierarchy, interconnect).
• Lead performance analysis using simulators, RTL.
• Help develop and validate performance models (cycle‑accurate, trace‑driven, statistical).
• Characterize workloads (SPEC, server, client, AI/ML, cloud, internal traces) and translate findings into architectural requirements.
• Identify performance bottlenecks and propose data‑driven optimizations.
• Drive architecture‑to‑implementation alignment with design team.
• Collaborate with compiler, OS, and system architects on cross‑stack performance issues.
• Mentor senior and staff engineers; provide technical leadership across projects.
• Work leading to patents and publication.

What You Bring

• Master’s with 18+ years of experience in Computer Engineering, Computer Science, or related field.
• or PhD with 15+ years of experience preferred.
• 10+ years of experience in CPU microarchitecture and/or performance engineering.
• Experience with RISC‑V, ARM or X86 architectures.
• Strong understanding of:
  • Out‑of‑order execution, branch prediction, pipelines, and speculation.
  • Cache coherence, memory systems, prefetching, and NUMA effects.
• Hands‑on experience with architectural simulators (like gem5).
• Strong programming skills in C/C++ and Python.
• Familiarity with compiler optimizations and hardware/software co‑design.
• Familiarity with SIMD / Vectors / VME for AI inference workloads.
• Experience analyzing large performance datasets and traces.
• Proven ability (Tapeout / Patents / Publications) to influence architecture/microarchitectural decisions through quantitative analysis.

Preferred Qualifications

• Background in power/performance/area (PPA) trade‑off analysis.
• Experience with SIMD/Vectors.
• Experience with compiler optimizations and hardware/software co‑design.
• Prior technical leadership at Senior Staff or Principal level.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• You approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

What We Offer

• Pay range: $219,000 – $351,000 USD for all U.S. locations. Incentive opportunities reward performance.
• Diverse benefits centered on wellbeing: medical, dental, vision, 401k, and an inclusive rewards plan.
• Give back: charitable giving match and community involvement opportunities.
• Enjoy time away: 4+ weeks of paid time off a year plus holidays and sick leave.
• Care for family: stipend for fertility care or adoption, medical travel support, virtual vet care for pets.
• Prioritize emotional wellness: on‑demand apps and free confidential therapy sessions.
• Stay fit: onsite Café and gym, virtual classes.
• Embrace flexibility: flexible environment to find balance.

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.