Principal Design Verification Engineer – CPU Core Frontend

SiFive; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Healthcare

Equity

Job summary

SiFive is seeking a senior verification engineer to lead frontend verification for high‑performance CPU cores. You will own verification planning, strategy, and execution for frontend microarchitecture including branch prediction and instruction fetch, with escalation to signoff readiness.

The role emphasizes mentoring, reusable DV infrastructure, and cross‑functional collaboration with architects. You will drive coverage, debug complex frontend issues, and guide teams across performance and

Qualifications

• Bachelor's, master's, or PhD in Electrical/Computer Engineering or CS.
• 12+ years in CPU/core or SoC functional verification for principal level.
• 8+ years verifying memory management units in high‑performance CPU cores.
• Direct experience with out‑of‑order CPU core verification and CPU frontend verification.
• Deep expertise in frontend verification, especially branch prediction and instruction fetch.
• Strong knowledge of verification flow, test planning, stimulus, failure analysis, and coverage closure.
• Strong debugging skills and ability to translate architectural intent into verification strategy.
• Strong software and scripting fundamentals for scalable DV infrastructure.

Responsibilities

• Lead verification planning and execution for CPU frontend functionality.
• Define verification strategy, test plans, checkers, scoreboards, and coverage models.
• Drive verification of branch prediction structures and fetch behavior.
• Collaborate with architects to review specs and improve frontend debugability.
• Oversee verification closure, coverage analysis, bug triage, and signoff readiness.
• Mentor engineers and shape reusable DV infrastructure for future cores.

Skills

Frontend verification

Branch prediction

Instruction fetch

DV infrastructure

Scripting (Python/Bash)

Mentoring

Debugging

CPU microarchitecture

Education

BS/MS/PhD in EE/CE/CS

Tools

Python

Shell scripting

C/C++

Job description

Responsibilities

• Lead verification planning and execution for CPU frontend functionality in a high-performance out-of-order core, with ownership spanning branch prediction and instruction fetch behavior.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for frontend microarchitecture and its corner cases.
• Drive verification of branch prediction structures and flows, including direction prediction, indirect target prediction, return prediction, predictor update/training behavior, redirect generation, recovery, and interaction with global history or related predictor state.
• Drive verification of instruction fetch behavior, including fetch packet correctness, PC sequencing, fetch ordering, ITLB/translation interactions, exception reporting, cache-related fetch behavior, and redirect handling after misprediction or flush conditions.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, and improve frontend debugability and verification completeness.
• Drive block-level and core-level verification closure for frontend features, including coverage analysis, gap identification, bug triage, and signoff readiness.
• Apply the right verification method for the problem, including simulation, formal techniques, and emulation where appropriate for high-risk or hard-to-observe frontend behaviors.
• Mentor engineers across the organization and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification appropriate for a Principal/T6 role.
• 8+ years of direct experience verifying memory management units in high-performance CPU cores, including hypervisor, virtualization, and guest virtualizations.
• Direct experience with out-of-order CPU core verification and strong understanding of CPU microarchitecture.
• Deep expertise in CPU frontend verification, especially branch prediction and instruction fetch verification.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and ability to translate architectural intent into an effective verification strategy and execution plan.
• Strong software and scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.

Preferred Qualifications

• Experience verifying advanced frontend architectures or decoupled fetch/prediction pipelines in high-performance CPU cores.
• Experience with branch prediction microarchitecture such as BTB-style structures, target prediction, return prediction, global-history-based prediction, predictor training, and misprediction recovery.
• Experience using formal verification to target bounded, control-heavy, or interface-sensitive frontend problems.
• Experience using emulation or other acceleration techniques to improve turnaround on large CPU verification workloads.
• Experience collaborating across architecture, performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring, methodology influence, and cross-team execution on complex CPU verification efforts.

What Success Looks Like

• Frontend verification plans capture real architectural and microarchitectural risks early and completely.
• Difficult branch prediction, fetch, redirect, and recovery bugs are found early, debugged efficiently, and closed with durable solutions.
• Verification quality improves across the broader CPU DV organization through stronger methodology, reusable infrastructure, and clear technical leadership.
• Architecture, design, and DV teams rely on this engineer to solve the most complex frontend verification challenges in high-performance CPU development.

Benefits

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The position also offers a comprehensive, competitive benefits package that may include healthcare, retirement plans, paid time off, and additional perks.

Additional Information

Security and background checks are required, and proof of right to work in the United States of America must be provided. The company must verify eligibility for access to export-controlled technology under applicable law, or obtain necessary licenses if not already authorized.

Equal Opportunity Employer

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E-Verify employer, we use this system to confirm employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre‑screen job candidates and will comply with all E-Verify regulations.