Principal CAD Engineer

Ampere Computing LLC; Santa Clara (CA); On-site; USD 180,000 - 270,000; Full time

Job summary

Ampere Computing LLC in Santa Clara, CA is seeking an experienced Principal CAD Engineer to advance high-performance CPU design through robust physical design flows and PPA optimization. You will drive synthesis and physical design methodology in a small but growing processor-design group.

Collaborate with implementation and physical design teams to optimize PPA metrics, analyze impact of tech changes on chip power and performance, and balance timing, area, and routability across multiple

Qualifications

• Experience developing physical design flows for high-performance designs.
• Ability to contribute to PPA methodology changes across projects.
• Collaborate with implementation and physical design teams to optimize PPA metrics.

Responsibilities

• Drive development and continuous improvement of synthesis and physical design methodology with a focus on maximizing PPA.
• Collaborate closely with implementation and physical design teams to optimize PPA metrics across multiple projects.
• Analyze the impact of technology and design changes on PPA at block and full chip level.
• Identify PPA bottlenecks and develop solutions that balance timing, area, power and routability.

Skills

Physical design

Synthesis

PPA optimization

EDA tools

Collaboration

Tools

EDA tools

Job description

Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AIcompute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

Join us at Ampere and work alongside a passionate and growing team-we'dlove to have you apply!

About the role:

We are looking for an experienced Principal CAD Engineer to join a small but growing Processor Design group, advancing the art of high-performance implementation and physical design. Ideal candidates will develop and maintain physical design flows for high performance designs and contribute to PPA related methodology changes across multiple projects and technology nodes.

What you'll achieve:

• Drive development and continuous improvement of synthesis and physical design methodology with a focus on maximizing Power, Performance and Area (PPA)
• Collaborate closely with implementation and physical design teams to optimize PPA metrics across multiple projects
• Analyze the impact of technology and design changes on PPA at block and full chip level
• Identify PPA bottlenecks and develop solutions that balance timing, area, power and routability