Principal ASIC Synthesis and Timing Engineer

K2 Space Corporation; Los Angeles (CA); On-site; USD 190,000 - 280,000; Full time

Benefits offered by this job

Paid time off

Medical/dental/vision coverage

Life insurance

Paid parental leave

Job summary

K2 Space Corporation in Los Angeles is seeking a Principal ASIC Synthesis and Timing Engineer. This role involves leading the implementation of complex SoCs for next-generation satellites and systems, collaborating closely with various teams to ensure timing closure and design integration. The ideal candidate has over 10 years of ASIC design experience and a strong background in RTL-to-GDSII flows. The company offers a competitive salary ranging from $190,000 to $280,000 along with a comprehensive benefits package.

Qualifications

• 10+ years of experience in ASIC design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools.
• Strong hands-on experience with timing closure and low power implementation.

Responsibilities

• Own the complete RTL-to-Synthesis flow.
• Collaborate with front-end and verification teams.
• Manage external physical design partners.
• Develop an end-to-end formal verification methodology.

Skills

RTL-to-GDSII flow expertise

Timing closure

Low power implementation

Communication skills

Leadership

Education

B.S. or M.S. in Electrical Engineering

Tools

Synopsys

Cadence

Siemens

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today’s and tomorrow’s massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we’d love for you to apply.

The Role

We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next‑generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis—and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence of schedule and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state‑of‑the‑art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting‑edge SoCs that will fly in space.

Responsibilities

• Own the complete RTL‑to‑Synthesis flow: Do synthesis at block and top level, work with physical design team to integrate the floorplanning information for physical synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front‑end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign‑off with foundry‑qualified tools.
• Own Lint, CDC and UPF checks and drive collaboration to close out issues.
• Develop an end‑to‑end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the post‑layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring‑up and debug through close collaboration with post‑silicon and test teams.
• Support your product through production and spaceflight.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands‑on experience with timing closure, IR drop analysis, low power implementation and ECO implementation.
• Deep understanding of physical design constraints for multi‑clock, multi‑voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Able to resolve formal verification issues.
• Able to analyze and fix VCLP issues regarding UPF.
• Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, Low power checker to validate UPF.
• Familiarity with DFT integration, STA sign‑off with functional ECO implementation.
• Excellent communication, leadership, and cross‑functional collaboration skills.
• Act as technical leader and subject‑matter expert helping to teach, grow, and mentor others in the team.

Nice to Have

• Exposure to radiation‑hardened or space‑qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate‑All‑Around technologies.
• Experience working in cross‑functional, geographically distributed teams.

Compensation And Benefits

• Base salary range for this role is $190,000 – $280,000 + equity in the company.
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level.
• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

Export Compliance

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.