Principal Digital ASIC Design Engineer

K2 Space Corporation; United States; On-site; USD 190,000 - 285,000; Full time

Benefits offered by this job

Equity in the company

Comprehensive benefits package

Paid parental leave

Job summary

K2 Space Corporation is looking for a Principal Digital ASIC Design Engineer to oversee the design and integration of advanced digital subsystems for wireless SoCs. This role requires significant experience in RTL design, a strong background in DSP development, and the ability to lead complex verification processes. The position is based in the United States, offering a competitive salary range of $190,000 – $285,000 along with a comprehensive benefits package including paid time off and medical coverage.

Qualifications

• 10+ years of experience in digital ASIC design, with significant ownership of complex subsystems.
• Experience in closing full-chip and subsystem timing.
• Solid understanding of SoC design flows including clock/power domain crossing.

Responsibilities

• Own the architecture and implementation of key digital blocks in wireless SoCs.
• Collaborate with system architects to translate high-level DSP algorithms.
• Lead verification planning and validation of complex digital subsystems.

Skills

RTL design (SystemVerilog or Verilog)

Micro-architecture definition

DSP development for wireless communication

Strong debugging and problem-solving skills

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Tools

EDA tools (Synopsys, Cadence, Siemens)

Job description

The Role

We are seeking a highly skilled Principal Digital ASIC Design Engineer to lead the design and implementation of digital subsystems for advanced wireless SoCs. You will be part of a collaborative design team developing state‑of‑the‑art mixed‑signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and manufactured satellites ever deployed in space.

In your first six months you will architect, develop, and implement new SoC sub‑systems for satellite communications and beyond. In your first two years you will have flown your sub‑system in space and developed cutting‑edge mixed‑signal SoCs.

Responsibilities

• Own the architecture, microarchitecture, RTL implementation, and integration of key digital blocks in wireless SoCs.
• Collaborate with system architects to translate high‑level DSP algorithms into efficient hardware implementations.
• Drive end‑to‑end development of DSP systems (e.g., filters, beamformers, FFT/IFFT engines).
• Convert chip specifications into RTL using internal IPs and external IPs.
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug.
• Partner with analog/mixed‑signal teams to define digital‑analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration.
• Lead or contribute to verification planning and validation of complex digital subsystems.
• Participate in chip bring‑up and lab validation of complex digital subsystems.
• Support your product through production and spaceflight.
• Act as a technical leader and subject‑matter expert, helping to teach, grow, and mentor others in the team.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of relevant industry experience in digital ASIC design, with significant ownership of complex subsystems.
• Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools.
• Experience in micro‑architecture definition from architecture guideline and model analysis.
• Experience in closing full‑chip and subsystem timing working with synthesis and static analysis teams.
• Experience with DFT tools for scan and BIST insertion.
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification.
• Experience developing and integrating DSP blocks for wireless communication (e.g., OFDM, MIMO, channel estimation, DFE, etc.).
• Strong experience with EDA tools for design, synthesis, static timing analysis, and power analysis (e.g., Synopsys, Cadence, Siemens tools).
• Strong debugging, problem‑solving, and communication skills.

Nice to Have

• Prior experience in wireless SoC development (e.g., cellular, Wi‑Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes.
• Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM’s AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART.
• Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL.
• Experience working with FEC, baseband PHYs, or digital beamforming architectures.
• Knowledge of digital calibration and control of RF/mixed‑signal front ends.
• Exposure to hardware‑software co‑design and embedded process integration.
• Experience working in cross‑functional, geographically distributed teams.

Compensation And Benefits

• Base salary range for this role is $190,000 – $285,000 + equity in the company.
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level.
• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks.

If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non‑traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.”

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R.

• 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.