Principal Architect, AI Performance Modeling

Entrada Ventures; California (MO); Hybrid; USD 170,000 - 250,000; Full time

Job summary

d-Matrix is seeking a Principal Architect, Performance Analysis and Modeling to analyze and model performance across the hardware/software boundary of our AI inference accelerators in Santa Clara, CA. The role focuses on emerging hardware technologies and workloads, building analytical models and simulators for current and future silicon.

You will work with Hardware Design, Compiler, Inference Server and Kernels teams to translate workload analysis into concrete inputs and surface opportunities

Qualifications

• BSEE or higher with 6+ years in industry or MSEE with 4+ years.
• Strong knowledge of computer architecture and performance modeling.
• Proficient in C/C++ or Python with experience in analytical models or simulators.

Responsibilities

• Analyze emerging ML workloads and multi-model workloads to identify performance-relevant properties.
• Build and maintain analytical performance models projecting behavior on current and future hardware.
• Develop and extend simulators to support performance analysis of HW/SW features.
• Collaborate with hardware design, compiler, inference server, kernel, and product teams to validate modeling assumptions.
• Track ML architecture research and incorporate findings into modeling work.
• Propose HW/SW improvements based on modeling results and workload analysis.
• Document methodologies and findings for reuse across the architecture team.

Skills

Computer architecture

HW/SW co-design

Performance modeling

ML fundamentals (DNNs)

C/C++ or Python

Analytical models/simulators

Cross-team collaboration

Education

BSEE with 6+ years

MSEE with 4+ years

Job description

d-Matrix is seeking a Principal Architect, Performance Analysis and Modeling to analyze and model performance across the hardware/software boundary of our AI inference accelerators in Santa Clara, CA. The role focuses on emerging hardware technologies and workloads, building analytical models and simulators for current and future silicon.

You will work with Hardware Design, Compiler, Inference Server and Kernels teams to translate workload analysis into concrete inputs and surface opportunities