Pre-Silicon Verification Engineer

Sumeru Solutions; Santa Clara (CA); On-site; USD 60,000 - 100,000; Full time

Job summary

A leading IT services provider is seeking a Pre-Silicon Verification Engineer in Santa Clara, CA. The ideal candidate will have 5-7 years of experience in SOC/CPU microarchitecture and pre-silicon verification, along with strong skills in validation tools like Verilog and System Verilog. Responsibilities include power management verification using SYNP UPF flow. This is a long-term contract position offering competitive compensation.

Qualifications

• Five to seven years of pre-silicon verification experience.
• Familiarity with power management flows.
• Experience in automation using Perl is desirable.

Responsibilities

• Verification of power management using SYNP UPF flow.
• Work in Santa Clara.
• Demonstrate problem-solving and innovative methods.

Skills

SOC/CPU microarchitecture skills

Verification background

Logic design and validation tools

Verilog/System Verilog

C/C++ knowledge

Automation using Perl

Education

Bachelor's degree

Tools

Synopsys VCS

Job description

Sumeru has been in the IT Business for more than a decade. Clients across 22 countries turn to us for their Web Application Services, Information Security and Business Process Management needs. We are Microsoft Gold Certified partners and also an ISO 270001 certified company.

Job Description

We are sourcing for Pre-Silicon Verification Engineer with one of our Direct Client in Santa Clara, CA. Please go through to the job description below and of you feel comfortable with the Required skills and responsibilities, please reply me back with your updated word doc resume and Table with your details to vinay.shrivas AT sumerusolutions.com or contact me for more details at 571-250-5780.

Job Title : Pre-Silicon Verification Engineer

Project Duration : Long term (6 – 12 + months Contract )

Responsibilities

• Importantly someone who is familiar with power management verification (we use SYNP UPF flow).
• This person should be able to work in Santa Clara and ASAP (preferably next week itself).

Submission

• Candidate Name
• Present location (city, state or ZIP)
• Preferred Base Location
• Work Authorization
• Tel No
• Email ID
• *Joining availability (post-selection)
• Overall relevant experience of candidate
• Expected Rate/Salary - $$/HR/K
• Do you have 4 year degree (Y/N)
• Ready to Travel (Y/N)
• Where would you stand in scale of 1-10 for this req

Qualifications

• Strong SOC/CPU microarchitecture and/or system level skills with five to seven years of pre-si verification background
• Experience with logic design and validation tools and methodologies including: Verilog, System Verilog, OVM/UVM, Synopsys VCS
• Familiarity of power management flows
• Knowledge of assertion based languages and/or methodology and C/C++ would be an added advantage
• Knowledge of emulation platforms a plus
• Experience in automation using Perl is desirable
• Demonstrate capability to ramp on any Industry standard device protocols and architecture
• Need to have demonstrated excellence in problem solving and resolution through innovative methods in environment/tools capabilities, test plan and test development, debug, automation, etc.

Additional Information

All your information will be kept confidential according to EEO guidelines.