Post-Silicon Validation, Senior Staff Engineer

Synopsys Inc; Hillsboro (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys Inc. is seeking a skilled post-silicon validation engineer to own UCIe die-to-die interface IP validation, create lab automation software, and lead complex debugging across design, packaging, and protocol layers.

You will also support customer bring-up and develop characterization methods for challenging die-to-die links, while mentoring peers. The role emphasizes strong software engineering, multi-language development, and hands-on lab work in a cutting-edge environment focused on AI

Qualifications

• BS or MS in Electrical/Computer Engineering with relevant experience.
• Experience in post-silicon validation, characterization, and debugging of high-speed interfaces.
• Strong software engineering practices and multi-language development (Python/C/C++).

Responsibilities

• Own post-silicon validation and characterization strategy for UCIe die-to-die interface IP.
• Architect and develop lab automation software spanning Python, C, and C++.
• Lead complex debug efforts spanning design, packaging, and protocol layers.
• Support customer silicon bring-up and debugging in lab environments.
• Develop characterization methods for die-to-die links with limited access.
• Design UIs and data tools for customer evaluations and internal reporting.
• Mentor teammates and establish measurement methodologies.

Skills

Python

C++

C

Lab automation

UI development

Debugging

Signal integrity

UCIe

Data analysis

Software design

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

GitLab

Jira

Confluence

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the lab where silicon meets reality, where the design that looked perfect in simulation sometimes does something completely unexpected at power-on, and you have learned to love that moment. Not because it is easy, but because finding the answer requires the kind of deep technical thinking that most people avoid.

You are the engineer who gets called when a customer's chiplet link will not train and no one else can figure out why. You do not panic. You methodically work through the protocol stack, the package channel, the firmware state machine, and the on-die instrumentation until you isolate the variable that matters.

You write code that performs reliably in an R&D lab, including when rapid development is needed to unblock critical debug. You balance speed with sound software engineering, knowing when a focused debug script is appropriate and when the solution requires maintainable, well-structured code that can evolve over time. Python for automation, C++ for performance-critical control loops, and you know when to reach for which one. You have architected software frameworks that other engineers depend on, and you take that responsibility seriously because bad infrastructure creates bad data.

Working with customers does not intimidate you. You have debugged silicon in someone else's lab, explained what you found to their engineering team, and left them confident that the issue is understood and fixable. At Synopsys, you will set the technical direction for UCIe validation, mentor engineers who want to become you, and solve problems that matter to the future of chiplet-based systems.

What You'll Be Doing

• Own the post-silicon electrical validation and characterization strategy for UCIe die-to-die interface IP, from test plan definition through silicon sign-off, determining what gets measured, how it gets measured, and what constitutes a pass
• Architect and develop the software solutions the team uses for lab automation, result processing, and silicon debug, spanning Python, C, and C++, including frameworks that handle instrument control, data capture, and automated test execution
• Lead complex debug efforts that span circuit design, package and interposer channel behavior, link training firmware, and protocol layer interactions, driving issues to root cause when the failure mode is ambiguous and the data is incomplete
• Support customers directly with the bring up and debug of their silicon, including sideband and mainband link training, lane repair and reversal, degraded mode operation, and chiplet interoperability, delivered through on-site lab visits and remote correlation sessions
• Develop characterization methodology for die-to-die links where direct probe access is limited, making effective use of on-die instrumentation, eye margining, built-in monitors, and traditional bench equipment like oscilloscopes, BERTs, and spectrum analyzers
• Design and develop UIs and data presentation tools used for customer evaluations, marketing demonstrations, and internal reporting, ensuring that complex silicon behavior is communicated clearly to technical and non-technical audiences
• Review and approve the work of other validation engineers, provide technical mentorship and coaching to junior and mid-level team members, and establish the measurement and correlation methodology the broader team adopts

The Impact You Will Have

• Ensure the reliability and performance of Synopsys' UCIe die-to-die interface IP, directly contributing to the success of the multi-die and chiplet-based systems our customers are building for AI, HPC, and data center applications
• Deliver validation results and methodology that have measurable impact on department targets, including silicon sign-off schedules and time-to-market for new IP releases
• Establish the technical foundation and tooling that the validation team builds upon, raising the capability and efficiency of the discipline as a whole
• Shorten debug cycles on complex, first-of-a-kind silicon issues that would otherwise jeopardize product schedules and customer commitments
• Strengthen customer confidence through credible, well-correlated silicon data and compelling evaluation demonstrations that prove the IP works in real systems
• Accelerate customer time-to-market by getting their silicon up and running quickly and resolving field issues before they elevate design respins or schedule delays
• Grow the next generation of validation engineers through mentorship, technical review, and coaching, building the bench strength the team will need as UCIe adoption scales

What You'll Need

• Bachelor's degree in Electrical Engineering or Computer Engineering with a minimum of 8 years of related experience, or a Master's degree with a minimum of 6 years of related experience
• Extensive hands-on experience in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP; direct experience with UCIe or another die-to-die interface is strongly preferred, and high-speed SerDes experience is applicable
• Working knowledge of the UCIe specification, including the PHY and D2D adapter layers, link initialization and training, sideband operation, and standard versus advanced package considerations
• Advanced software development capability across multiple languages including Python, C, and C++, with a strong command of software engineering best practices, data structures, and algorithms; experience with software version control systems such as GitLab and with issue and task tracking through Jira and Confluence is a plus
• Demonstrated experience architecting complex software projects, including lab automation frameworks and Python UI development, that other engineers depend on
• Expert-level debug experience with high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers, and the ability to extract meaningful signal integrity and protocol-level insights from noisy lab data
• Experience supporting customer silicon bring up and debug, including working in a customer lab environment and communicating findings directly to external engineering teams; experience with Signals & Systems concepts, transmission line theory, and high-speed link analysis applied to package, interposer, and substrate channels is a plus

Who You Are

• A sophisticated technical professional who applies advanced knowledge and wide-ranging experience to resolve complex problems in creative and effective ways, not by following a checklist but by understanding the system deeply enough to know where to look
• A seasoned lab engineer who is recognized as a go-to resource for difficult silicon debug, whether the silicon is ours or a customer's, and who can diagnose problems under schedule pressure in an unfamiliar lab without losing your cool
• A credible technical presence in front of customers, comfortable presenting data that may not be what they wanted to hear and explaining what it means and what comes next in terms they can act on
• A mentor who invests in the growth of junior engineers and elevates the technical standards of the team, not by doing the work for them but by teaching them how to think through the problem
• An effective communicator who can convey complex technical information to designers, management, and customers alike, adjusting the level of detail and framing to match the audience without losing the nuance
• A collaborative influencer who can justify an approach and gain the cooperation of other groups across the department, even when your recommendation requires them to change their plan

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.