Post-Silicon Validation Engineer — High‑Speed Memory

Carra; Tempe (AZ); On-site; USD 90,000 - 130,000; Full time

Job summary

Renesas Electronics is seeking an engineer with a background in post-silicon validation and characterization. The role involves silicon bring-up, validation, and collaboration with design, system, and product engineering teams to ensure robust performance of high-speed memory interfaces.

The candidate will validate high-speed Rx/Tx paths, perform jitter analysis, generate eye diagrams using high bandwidth equipment, and develop automated test plans to ensure reproducible results.

Qualifications

• Master's degree in Electrical Engineering or related field.
• 1+ years hands-on lab experience in high-speed Analog and Mixed-signal devices.
• Understanding of signaling levels, termination architectures, and signal integrity tradeoffs.
• Familiarity with high-speed interface test equipment (BERT, High BW Oscilloscope, signal generators, etc.).
• Proficiency in Python for test automation and analysis.

Responsibilities

• Perform initial silicon bring-up and debugging.
• Validate high speed Rx and Tx paths, PLLs including jitter analysis and eye diagram using High Bandwidth Oscilloscopes, BERT and DDR5 tools.
• Develop, execute, and automate post-silicon validation and characterization test plans for critical electrical and timing parameters.
• Collaborate with designers and cross-functional partners to debug and optimize performance.
• Generate clear, consistent reports; maintain reproducible test methodologies.

Skills

Python scripting for test automation

Analytical and problem-solving

Lab experience in high-speed Analog &'

Education

Master's degree in Electrical Engineering

Tools

BERT

High Bandwidth Oscilloscope

Signal Generators

Compliance Software

Job description

Renesas Electronics is seeking an engineer with a background in post-silicon validation and characterization. The role involves silicon bring-up, validation, and collaboration with design, system, and product engineering teams to ensure robust performance of high-speed memory interfaces.

The candidate will validate high-speed Rx/Tx paths, perform jitter analysis, generate eye diagrams using high bandwidth equipment, and develop automated test plans to ensure reproducible results.