Pixel Design Engineer – Process R&D

OMNIVISION; Santa Clara (CA); On-site; USD 140,000 - 170,000; Full time

Job summary

A leading semiconductor company is seeking a Pixel Design Engineer in Santa Clara, California. This role involves optimizing pixel structures and developing innovative pixel technologies while collaborating with diverse teams. The ideal candidate has over 5 years of experience in pixel optimization and semiconductor processes, with strong skills in simulation methodologies. The position offers a competitive salary range of $140,000 to $170,000 based on experience and skills.

Qualifications

• 5+ years of experience in pixel optimization and performance enhancement.
• 5+ years in device-based technologies with CIS process experience preferred.
• Background in simulation tools and semiconductor device physics.

Responsibilities

• Optimize pixel structures for better performance and efficiency.
• Develop and validate simulation methodologies for CIS optimization.
• Collaborate to improve pixel characteristics and develop new architectures.
• Partner to model and optimize devices and components.

Skills

Pixel optimization

Simulation methodologies

Device-based technologies

Semiconductor processes

Cross-functional collaboration

Education

MSEE, MS in Physics or equivalent

PhD preferred

Job description

Role Overview

As a Pixel Design Engineer within the Process R&D team, you will work on innovation in pixel architecture and process optimization. You will play a key role in advancing simulation methodologies, developing next‑generation pixel technologies, and collaborating cross‑functionally to enable cutting‑edge imaging and display solutions.

Key Responsibilities

• Optimize pixel structures and fabrication processes to improve electrical / optical performance and efficiency.
• Develop, enhance, and validate simulation methodologies for CIS (CMOS Image Sensor) pixel optimization and system‑level modeling.
• Collaborate with process integration and design teams to improve pixel characteristics and develop new pixel architectures tailored to specific applications, including Phase Detect (PD), Dual Pixel Detection (DPD), Near‑Infrared (NIR), Time‑of‑Flight (ToF) and LCOS (Liquid Crystal on Silicon).
• Partner with system engineering and architecture teams to model and optimize devices, components, and full systems leveraging OVT sensors and display technologies.
• Contribute to next‑generation sensors and display performance through data‑driven modeling and cross‑functional innovation.

Qualifications

• 5+ years of experience in pixel optimization and performance enhancement.
• 5+ years of experience in device‑based technologies, including development of advanced semiconductor processes (CIS process experience strongly preferred).
• MSEE, MS in Physics, or equivalent required; PhD preferred.
• Background in simulation tools and semiconductor device physics.
• Demonstrated ability to work cross‑functionally in R&D environments.

Annual base salary for this role in California, US is expected to be between $140,000 - $170,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

EOE/Minorities/Females/Vet/Disability