Physical Design Verification Lead (7264)

TSMC - Taiwan Semiconductor Manufacturing Company Limited; San Jose (CA); On-site; USD 153,000 - 230,000; Full time

Benefits offered by this job

Comprehensive benefits

Extensive development opportunities

Market competitive pay

Job summary

A leading semiconductor company is seeking a highly experienced Physical Design Verification Lead in San Jose, California. The role involves ensuring the physical integrity of high-performance chip designs and requires expertise in Electronic Design Automation tools. Candidates should possess a Master’s degree and extensive experience in physical implementation and verification roles, especially with TSMC technology nodes. This position offers a competitive salary and the opportunity to work on cutting-edge technology that powers the next generation of semiconductor innovations.

Qualifications

• 10-20 years of hands-on experience in verification roles.
• Demonstrated expertise with major EDA tools and design flows.
• Proven experience with advanced technology nodes, specifically TSMC N7 or below.

Responsibilities

• Lead and execute end-to-end physical design verification.
• Collaborate closely with the STA team for timing closure.
• Optimize block-level floorplans and implement advanced strategies.

Skills

Expertise with EDA tools

Scripting languages proficiency (TCL, Perl, Python)

Chip integration experience

Education

Master’s degree in Electrical Engineering or related field

Tools

Innovus

ICC2

Calibre

Job description

Physical Design Verification Lead (7264)

Overview of Role
TSMC Technology Inc. is at the forefront of semiconductor innovation, delivering cutting‑edge solutions that power the next generation of technology. We are seeking a highly experienced and motivated Physical Design Verification Lead to join our dynamic team, working closely with a key customer on advanced designs in N2P/A14 technology nodes. This is an exceptional opportunity to drive critical verification efforts on state‑of‑the‑art technology nodes and contribute to successful production tapeouts.

Responsibilities
As a Physical Design Verification Lead, you will be a pivotal member of our team, responsible for ensuring the robust physical integrity and performance of high‑performance chip designs. You will lead comprehensive physical verification efforts from block‑level implementation through to final production tapeout, playing a crucial role in achieving silicon success. Your expertise will directly impact the quality and reliability of our advanced products.

• Lead and execute end‑to‑end physical design verification for CPU blocks, culminating in successful production chip tapeouts.
• Collaborate closely with the STA team to implement Engineering Change Orders (ECOs) for critical timing closure.
• Perform in‑depth analysis and resolution of Signal EM/Noise and Power IR/EM issues.
• Manage comprehensive analysis and cleanup for all physical verification checks, including DRC, LVS, ERC, and Antenna violations.
• Achieve final physical verification sign‑off across all design metrics.
• Oversee the implementation of customized Clock Tree Structures (CTS) and advanced Place & Route strategies.
• Optimize block‑level floorplans, meticulously analyzing and ensuring high‑quality design partitioning.
• Provide technical leadership and mentorship to junior engineers.

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10-20 years of hands‑on experience in physical implementation and verification roles.
• Demonstrated expertise with major Electronic Design Automation (EDA) tools (e.g., Innovus/ICC2, Calibre) and established design flows.
• Extensive experience in chip integration and sign‑off procedures.
• Proven experience with advanced technology nodes, specifically TSMC N7 or below.
• Proficiency in scripting languages, particularly TCL, Perl, and Python, for automation and flow enhancement.
• Ability and willingness to work full‑time at a customer site located in the South Bay area.

Preferred Qualifications

• Direct experience with TSMC N2 technology nodes.
• In‑depth knowledge of CPU implementation methodologies.
• Expertise in advanced timing sign‑off methodologies and techniques.
• A strong track record of successful production tapeouts for multi‑million gate designs.
• Prior experience leading physical verification efforts or small teams.

Company Description

• The world’s leading dedicated semiconductor foundry.
• The technology leader with a strong reputation for manufacturing excellence.
• Advancing semiconductor manufacturing innovations to enable the future of technology.

TSMC pioneered the pure‑play foundry business model when it was founded in 1987 and has been the world’s leading semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting‑edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC Technology Inc. may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC Technology Inc. obtaining any export license or other approval that may be required by the U.S. Government.

Diversity statement

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at [e-mail] . TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case‑by‑case basis.

Pay Transparency / Benefits statement

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $153,000 and $230,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.