Physical Design Engineer

Capgemini Engineering; Santa Clara (CA); On-site; USD 82,000 - 193,000; Full time

Benefits offered by this job

Paid time off

Health benefits

Retirement plan

Employee assistance programs

Job summary

Capgemini Engineering in Santa Clara, CA is seeking a seasoned Physical Design Engineer to advance complex digital/mixed-signal IC implementations through floor planning, placement, CTS, routing, and tape-out readiness. You will optimize power, area, and performance while collaborating with cross-functional teams across the design lifecycle.

Key qualifications include 10+ years in physical design, proficiency with LVS/DRC, CDC, STA, and parasitic delay analyses, and hands-on use of Virtuoso,

Qualifications

• 10+ years of experience in Physical Design, with hands-on IC implementation.
• Strong knowledge of physical design flows including floor planning, clock tree synthesis, place and route, and design closure.
• Experience with power-grid strategies and high-speed clock constraints to optimize performance, power and area.
• Familiarity with LVS/DRC, CDC, static timing analysis, and parasitic delay.
• Exposure to mixed-signal environments and analog/layout interaction.
• Hands-on experience with EDA tools such as Virtuoso, Calibre, RedHawk.

Responsibilities

• Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical-aware synthesis.
• Develop and implement power-grid strategies, high-speed clock constraints, and design specifications to support performance, power, and area goals.
• Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
• Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
• Support CDC, static timing analysis, parasitic-aware simulations, and timing closure activities using relevant EDA tools and methodologies.
• Contribute to tape-out readiness, including design sign-off, foundry interaction, and alignment with IC product development requirements.
• Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm

Skills

Physical design

Floor planning

Clock tree synthesis

Place and route

Design closure

Power-grid strategies

CDC

Static timing analysis

Parasitic delay

EDA tools

Tools

Virtuoso

Calibre

RedHawk

Job description

Location : This is an onsite role based in Santa Clara, CA.

About the job you’re considering

As a Physical Design Engineer, you will work on complex digital and mixed-signal designs across advanced process technologies, helping drive designs from implementation through verification and tape‑out. This role offers the opportunity to solve challenging physical design problems, collaborate with cross‑functional engineering teams, and support next‑generation IC product development using industry‑leading methodologies and tools.

Your role

As a Physical Design Engineer, you will support the implementation and optimization of advanced‑node semiconductor designs. Key responsibilities may include

• Lead or support physical design activities, including floor planning, placement, clock tree synthesis, routing, and physical‑aware synthesis.
• Develop and implement power‑grid strategies, high‑speed clock constraints, and design specifications to support performance, power, and area goals.
• Perform physical design verification and debug LVS and DRC issues at both chip and block levels.
• Collaborate with design, layout, verification, timing, and methodology teams to address implementation challenges across the design lifecycle.
• Support CDC, static timing analysis, parasitic‑aware simulation, and timing closure activities using relevant EDA tools and methodologies.
• Contribute to tape‑out readiness, including design sign‑off, foundry interaction, and alignment with IC product development requirements.
• Evaluate design tradeoffs related to power consumption, area, performance, layout complexity, and technology limitations for advanced process nodes(3nm /5nm/7nm

Your skills and experience

We are looking for candidates with strong physical design expertise and hands‑on experience in advanced semiconductor implementation. Ideal qualifications include

• Must have 10+ years of experience in Physical Design, with hands‑on expertise supporting complex digital or mixed‑signal IC implementation.
• Strong knowledge of physical design flows, including floor planning, clock tree synthesis, place and route, physical‑aware synthesis, and design closure.
• Experience developing power‑grid strategies and high‑speed clock constraints to support performance, power, and area goals.
• Working knowledge of physical verification methodologies, including LVS and DRC debug at chip and block levels.
• Familiarity with CDC, static timing analysis methodologies, SDF‑annotated simulations, and parasitic delay impact.
• Exposure to mixed‑signal design environments and the interaction between digital implementation and analog/layout requirements.
• Hands‑on experience with tools such as Virtuoso, Calibre, RedHawk, or similar EDA platforms.
• Understanding of design tape‑out processes, foundry requirements, and the semiconductor product development supply chain.
• Experience with advanced TSMC process nodes, such as 7nm through 2nm, is highly preferred.

The base compensation range for this role in the posted location is $82,082 to $193,440

Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.

The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.

These may include, but are not limited to Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.

It is not typical for candidates to be hired at or near the top of the posted compensation range.

In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.

Capgemini offers a comprehensive, non‑negotiable benefits package to all regular, full‑time employees.

In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include

• Paid time off based on employee grade (A-F), defined by policy Vacation 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
• Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
• Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
• Life and disability insurance
• Employee assistance programs
• Other benefits as provided by local policy and eligibility

Important Notice

Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini’s discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.

Disclaimers

Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.

Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process.

Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.