Physical Design and Verification Engineer

Neuralink; San Francisco (CA); On-site; USD 131,000 - 265,000; Full time

Benefits offered by this job

Medical, dental, vision insurance

RSUs

401(k) plan

Meals provided

Paid holidays

Parental leave

Flexible time off

Growth opportunities

Job summary

Neuralink is seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout and lead multi-physics verification for stacked-die systems.

This role sits at the intersection of block-level signoff and 3D system closure, collaborating with packaging, CAD, DFT, DV, and design teams to deliver robust, high-performance chips.

Qualifications

• 5+ years of physical design experience.
• RTL-to-GDSII experience on advanced nodes (7nm/5nm/4nm/3nm or comparable).
• Hands-on hierarchical/top-level implementation on large multi-million inst designs.
• Strong command of STA concepts (setup/hold, OCV/AOCV/POCV) and physical verification signoff.
• Proficiency with PnR and signoff tools and TCL scripting.

Responsibilities

• Define and execute the hierarchical partitioning strategy across block boundaries.
• Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs.
• Own the interface between block owners and top-level integration, including ILM/ETM generation and hierarchical ECO propagation.
• Manage die-to-die partitioning for 3D stacks and plan inter-die interfaces.
• Synthesize, floorplan, place, route, CTS, signoff, and multi-physics verification across the design flow.
• Correlate thermal, mechanical, and electrical effects into 3D signoff methodology.
• Develop, document, and automate PnR and signoff flows; collaborate with packaging, DFT, DV, and CAD teams.

Skills

RTL-to-GDSII

Hierarchical design

Scripting (TCL)

STA concepts

Physical verification

Education

BS in Electrical/Computer Engineering

MS preferred

Tools

Cadence Innovus

Cadence Genus

Cadence Tempus

Cadence Voltus

Synopsys ICC2

Fusion Compiler

PrimeTime

StarRC

Calibre

Job description

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

About the Role

We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure.

Key Responsibilities

Hierarchical Physical Design

• Define and execute the hierarchical partitioning strategy: block boundaries, feedthroughs, pin placement, and budgeting across levels of hierarchy.
• Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs.
• Own the interface between block owners and top-level integration, including abstract (ILM/ETM) generation, boundary timing, and hierarchical ECO propagation.
• Manage die-to-die partitioning for 3D stacks – assign logic to tiers, plan hybrid-bond / µbump / TSV interfaces, and align inter-die floorplans.

Block-level Implementation & Signoff

• Synthesis: Drive logic synthesis (constraints, DFT insertion, physical-aware synthesis), QoR analysis, and RTL-to-gate correlation.
• Floorplanning: Macro placement, power planning, congestion and timing feasibility, and pin/port optimization.
• Placement & Optimization: Standard-cell placement, timing-driven and congestion-driven optimization, useful-skew and multi-corner/multi-mode closure.
• CTS: Clock tree synthesis and clock distribution (including inter-die clocking for 3D), skew/latency balancing, and OCV/AOCV/POCV-aware clock closure.
• Routing: Detailed routing, DRC/LVS convergence, signal integrity (crosstalk) closure, and antenna/via optimization.
• Signoff: Static timing analysis (STA) across all corners/modes, physical verification (DRC/LVS/DFM), EM/IR (static and dynamic), and formal netlist equivalence.
• Thermal: Build and run thermal models for stacked dies; analyze junction temperatures, hotspot coupling between tiers, and thermal-aware placement; feed thermal gradients back into timing and reliability signoff.
• Mechanical: Perform warpage, stress, and CTE-mismatch analysis for stacked/bonded assemblies; validate bump/TSV/hybrid-bond mechanical integrity and assembly-induced reliability risks.
• IR / Power Integrity: Static and dynamic IR-drop analysis across the 3D power delivery network, including inter-die PDN, TSV/bump resistance, decap strategy, and package-aware PI closure.
• Correlate thermal, mechanical, and electrical effects such as thermal-induced timing derates and stress-induced device shifts into a coherent 3D signoff methodology.
• Develop, document, and automate PnR and signoff flows (scripting, regression, QoR tracking).
• Partner with packaging, design, DFT, DV, and CAD teams to align die/package/system co-design.
• Debug convergence issues and drive root-cause analysis across timing, physical, and multi-physics domains.

Required Qualifications

• BS/MS in Electrical/Computer Engineering (or equivalent) with 5+ years of physical design experience; MS preferred.
• Proven full-cycle RTL-to-GDSII experience on advanced nodes (7nm/5nm/4nm/3nm or comparable).
• Hands-on hierarchical/top-level implementation on large (multi-million instance) designs.
• Strong command of STA concepts (setup/hold, OCV/AOCV/POCV, MMMC) and physical verification signoff.
• Proficiency with industry PnR and signoff tools (e.g., Cadence Innovus/Genus/Tempus/Voltus, Synopsys ICC2/Fusion Compiler/PrimeTime/StarRC, Siemens Calibre) and TCL scripting.

Preferred / Differentiating Qualifications

• Direct experience with 3DIC / 2.5D / chiplet implementation: TSVs, µbumps, hybrid bonding, interposers.
• Multi-physics analysis experience with tools such as Ansys RedHawk-SC, Cadence Voltus/Celsius/Integrity 3D-IC, or Synopsys 3DIC Compiler.
• Familiarity with thermal-aware and stress-aware design closure and die/package co-analysis.
• Python/scripting for flow automation and data analysis; experience with regression/QoR frameworks.
• Knowledge of reliability signoff (EM, aging/self-heat, ESD) in a 3D context.

Expected Compensation:The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range:: $131,000 USD - $265,000 USD

What We Offer:

Full-time employees are eligible for the following benefits listed below.

• An opportunity to change the world and work with some of the smartest and most talented experts from different fields
• Growth potential; we rapidly advance team members who have an outsized impact
• Excellent medical, dental, and vision insurance through a PPO plan
• Paid holidays
• Meals provided
• Equity (RSUs) *Temporary Employees & Interns excluded
• 401(k) plan *Interns initially excluded until they work 1,000 hours
• Parental leave *Temporary Employees & Interns excluded
• Flexible time off *Temporary Employees & Interns excluded