wSoC Design Verification Engineer

Apple Inc.; Sunnyvale (CA); On-site; USD 129,000 - 195,000; Full time

Job summary

Apple Inc. seeks a Design Verification Engineer to verify pre-silicon RTL for block and top-level SoC in a wireless silicon environment.

You will architect UVM-based testbenches, integrate complex VIPs, and drive coverage-driven verification with multi-team collaboration across DV, architecture, firmware, and IP delivery groups. Lead efforts on low-power/clock domains and high-speed interfaces like PCIe, AXI/NOC, and memory subsystems.

Qualifications

• Bachelor of Science in Electrical Engineering or equivalent.
• Experience in ASIC DV or pre-silicon RTL verification is preferred.
• Strong HDL/UVM knowledge and pre-silicon verification experience.

Responsibilities

• Verify pre-silicon RTL for block and top-level SoC.
• Architect and integrate UVM-based testbenches and VIPs.
• Develop coverage-driven verification plans from specs.
• Collaborate with DV methodology architects to improve flow.

Skills

Excellent communication

Problem solving

Team player

Education

Bachelor of Science in Electrical Engineering or equivalent degree

Tools

UVM

OVM

PCIe

Bus Fabric

NOC

AHB

AXI bus

Job description

As part of our team, you will have the opportunity to verifying a set of complex SOCs. Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a large-scale SOC, different types of SOC architectures, many high speed layered protocols, methodologies on low power architecture, best-in-class DV methodology. You will able to gain knowledge on Wireless protocol, FW-HW interactions, complexities of multi-chip SOC debug architecture, etc. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SoCs! This position comes with responsibility for pre-silicon RTL verification of block and top level SOC, comfortable with all areas of SoC Design Verification engineering, with an ability to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.

Description

Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes.Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF simulations, etcCreate coverage driven verification plans from specifications, review and refine to achieve coverage targets.Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level.Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design.Work closely with DV methodology architects to improve verification flow.

Minimum Qualifications

• Bachelor of Science in Electrical Engineering or equivalent degree

Preferred Qualifications

• Dedicated/hands-on ASIC DV experience
• Advanced knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM
• Some experience with formal verification is a plus
• Proven track record of working full ASIC cycle from concept to tape-out to bring-up
• Experience taping out large SOC systems with embedded processor cores
• Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification
• Low Power Verification experience is a plus
• Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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