Photonic Engineer, Senior

Qualcomm; Santa Clara (CA); On-site; USD 139,000 - 209,000; Full time

Job summary

Qualcomm Atheros, Inc. seeks a photonic IC designer to define and develop photonic integrated circuits for high-speed interconnect and DWDM transceivers.

You will use 3D simulations, FDTD/INTERCONNECT tools, and PDKs to drive from concept to tape-out, collaborating with cross-functional teams and applying AI-assisted automation. The role requires advanced degrees or extensive PIC experience, hands-on with Lumerical, Cadence Virtuoso, and Python, plus a track record of silicon-photonics tape-outs

Qualifications

• Bachelor's degree in EE, Physics, Optics, or related field with 5+ years of PIC design experience, OR
• Master's degree in EE, Physics, Optics, or related field with 3+ years of PIC design experience, OR
• PhD in EE, Physics, Optics, or related field with 1+ year of PIC design experiences.
• 2+ years hands-on with: Lumerical (FDTD, MODE, CHARGE, INTERCONNECT), and any layout editor/viewer (Cadence Virtuoso, KLayout, or equivalent), and Python.
• Hands-on design experience with silicon-photonics foundry PDKs.
• System-level understanding of optical link budgets, DWDM channel plans, OMA/TDECQ, and transceiver power allocation.

Responsibilities

• Design active (MRM, MZM, photodetectors) and passive (edge/grating couplers, power splitters, wavelength MUX/DEMUX) photonic devices from spec through tape-out using foundry PDKs and 3D structure optical simulation.
• Perform 3D photonic simulation (FDTD, MODE, INTERCONNECT, and CHARGE for carrier/electro-optic effects) to validate device performance and iterate to target specs.
• Develop and maintain script-based workflows — leveraging AI-assisted tooling — to automate parameter sweeps, layout generation, and measurement-data processing.
• Review and sign off on PIC physical layouts produced by the dedicated layout engineer from physical design team.
• Collaborate with other PIC designers, EIC designers, and package teams to run co-simulations. Align interface specs, and validate electro-optical performance in the full DWDM transceiver system.
• Execute and interpret post-fabrication characterization lab testing.
• Close the simulation-to-hardware loop by correlating characterization data with models and proposing corrections.
• Participate in cross-functional design reviews spanning component performance, tape-out readiness, and system link budget.
• Maintain internal technical documentation: design specs, simulation methodology, characterization reports, and tape-out checklists.
• Track silicon photonics, CPO, and DWDM transceiver developments, and apply emerging techniques to improve design quality and time-to-tape-out.

Skills

PIC design

Lumerical

Python

Cadence Virtuoso

3D optical simulation

Foundry PDKs

DWDM

Optical transceivers

Tape-outs

Co-Packaged Optics

Education

Bachelor’s degree in EE/Physics/Optics

Master’s degree in EE/Physics/Optics

PhD in EE/Physics/Optics

Tools

Lumerical

Cadence Virtuoso

KLayout

Job description

Company

Qualcomm Atheros, Inc.

Job Area

Engineering Group, Engineering Group > RFIC Design

General Summary

Define, design, and develop photonic integrated circuits for next-generation silicon photonics platforms targeting high-speed optical interconnect and DWDM transceiver applications. Perform photonic device design covering both active components and passive components using 3D structure simulation tools and foundry PDKs. Collaborate cross-functionally with other designers, and systems teams in a DWDM transceiver product project. Utilize script-based workflow with AI to automate simulation, layout generation, and data analysis. Work with testing engineers on post-fabrication device characterization in the lab to validate designs and close the loop between simulation and hardware.

Required for This Role

• Bachelor's degree in EE, Physics, Optics, or related field with 5+ years of PIC design experience, OR
• Master's degree in EE, Physics, Optics, or related field with 3+ years of PIC design experience, OR
• PhD in EE, Physics, Optics, or related field with 1+ year of PIC design experiences.
• 2+ years hands-on with: Lumerical (FDTD, MODE, CHARGE, INTERCONNECT), and any layout editor/viewer (Cadence Virtuoso, KLayout, or equivalent), and Python.
• Hands-on design experience with silicon-photonics foundry PDKs
• System-level understanding of optical link budgets, DWDM channel plans, OMA/TDECQ, and transceiver power allocation.

Preferred Qualifications

• 2+ years of Co-Packaged Optics (CPO) design experience — chip-to-chip optical coupling, CPO-specific constraints, or tape-out in a CPO-targeted node.
• 2+ years of PIC-EIC co-design — joint optimization for high-speed transceivers, including driver/TIA co-simulation with active photonic devices.
• System-level photonic simulation tools: VPI Photonics, Lumerical Zemax OpticStudio, or equivalent.
• DWDM wavelength control loops, thermal tuning, closed-loop resonance lock for ring-modulator transmitters.
• Track record of photonic tape-outs (MPW or full-reticle) with post-silicon characterization closure.
• Publication record or patent filings in integrated photonics.

Principal Duties and Responsibilities

• Design active (MRM, MZM, photodetectors) and passive (edge/grating couplers, power splitters, wavelength MUX/DEMUX) photonic devices from spec through tape-out using foundry PDKs and 3D structure optical simulation.
• Perform 3D photonic simulation (FDTD, MODE, INTERCONNECT, and CHARGE for carrier/electro-optic effects) to validate device performance and iterate to target specs.
• Develop and maintain script-based workflows — leveraging AI-assisted tooling — to automate parameter sweeps, layout generation, and measurement-data processing.
• Review and sign off on PIC physical layouts produced by the dedicated layout engineer from physical design team.
• Collaborate with other PIC designers, EIC designers, and package teams to run co-simulations. Align interface specs, and validate electro-optical performance in the full DWDM transceiver system.
• Execute and interpret post-fabrication characterization lab testing.
• Close the simulation-to-hardware loop by correlating characterization data with models and proposing corrections.
• Participate in cross-functional design reviews spanning component performance, tape-out readiness, and system link budget.
• Maintain internal technical documentation: design specs, simulation methodology, characterization reports, and tape-out checklists.
• Track silicon photonics, CPO, and DWDM transceiver developments, and apply emerging techniques to improve design quality and time-to-tape-out.

Level of Responsibility

• Works under some supervision, with high independence for component-level design decisions.
• Provides technical guidance and layout-review feedback to layout engineers and junior team members.
• Owns design deliverables; errors may impact the tape-out schedule and require re-simulation or a re-spin.
• Communicates technical status, simulation results, and characterization findings to EIC designers, packaging engineers, and systems architects.
• Works within the tape-out schedule, reticle area budget, and PDK constraints.
• Has meaningful influence on component-level architecture and platform-direction discussions.
• Completes multi-step tasks spanning simulation, layout, and characterization, and prioritizes parallel workstreams.
• Exercises engineering judgment when simulation, PDK, or characterization data is incomplete or conflicting.
• Applies inductive and deductive problem-solving to diagnose simulation-versus-measurement discrepancies.

EDA Tools

• Must: Lumerical (FDTD, MODE, INTERCONNECT), any layout editor/viewer (Cadence Virtuoso, KLayout, or equivalent), Python or equivalent
• Optional: MATLAB, VPI Photonics, Lumerical Zemax OpticStudio

Minimum Qualifications

• Bachelor's degree in Electrical Engineering with 3+ years of experience with designing RF/Analog circuits for wireless products (e.g., LNA's, PLL's) and 2+ years of ASIC design, verification, or related work experience.
• Master's degree in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience.
• PhD in Electrical Engineering or related field.
• 2+ years of academic or professional experience using two or more of the following software: CADENCE, Virtuoso, ADS.

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Pay range and Other Compensation & Benefits

$139,400.00 - $209,200.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.