RF/Analog IC Design Engineer

Qualcomm; Santa Clara (CA); On-site; USD 168,600 - 252,800; Full time

Job summary

Qualcomm Atheros, Inc. is seeking an experienced RFIC Design Engineer to define and develop complex RFICs for wireless applications.

The role emphasizes transistor-level design, simulation-driven verification, and collaboration with cross-functional teams to meet stringent performance targets for 4G, 5G, WLAN, BT and GPS standards. You will lead circuit-level specifications, drive module architecture, perform advanced RFIC engineering, and contribute to documentation and test plans.

Qualifications

• Bachelor's degree in Electrical Engineering with 3+ years of RF/Analog circuit design for wireless products and 4+ years of ASIC design/verification.
• Master's degree in Electrical Engineering with 4+ years of ASIC design/verification experience.
• PhD in Electrical Engineering with 2+ years of ASIC design/verification experience.
• 2+ years using two or more of Cadence, Virtuoso, or ADS.

Responsibilities

• Leads others and defines circuit-level specifications from system-level requirements.
• Develops module-level architecture and design of complex blocks using RFIC engineering practices.
• Runs simulations to evaluate circuit performance under various conditions.
• Collaborates with layout engineers for floorplan layout and physical verification.

Skills

RF/Analog design

ASIC design

Verification

Cadence tools

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence

Virtuoso

ADS

Job description

Company:

Qualcomm Atheros, Inc.

Job Area:

Engineering Group, Engineering Group > RFIC Design

General Summary:

Define, design and develop complex radio frequency integrated circuits in complex SoC’s and discrete RFIC’s. Perform radio signal path and circuit topology analysis and detailed transistor-level design of highly-integrated transceivers and associated blocks for wireless applications, 4G, 5G, WLAN, BT and GPS standards using advanced process technologies. Utilize complex analysis, simulation, engineering, science and mathematical principles to compose algorithm structures to solve problems. Assess processing requirements and select devices to meet requirements. Debug and assess performance of algorithms in actual application hardware.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering with 3+ years of experience with designing RF/Analog circuits for wireless products (e.g., LNA's, PLL's) and 4+ years of ASIC design, verification, or related work experience.
• Master's degree in Electrical Engineering or related field and 4+ years of ASIC design, verification, or related work experience.
• PhD in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience.
• 2+ years of academic or professional experience using two or more of the following software: CADENCE, Virtuoso, ADS.

Preferred Qualifications:

• 3+ years experience in the transistor level design of RF analog integrated circuits with a Master's degree in Electrical Engineering.
• Ph.D. in Electrical Engineering with internship or publication.
• 5+ years of experience in one or more of the following areas: Design of receiver and transmitter RF/Analog circuits, Design of high-performance RF frequency synthesizers, Digital control and signal processing, Product experience from conception, design, and product commercialization, Electro Magnetic simulation/modeling.
• 3+ years of experience working in a large matrixed organization.
• 1+ year of product experience with post silicon characterization.
• 1+ year in a technical leadership role with or without direct reports (only applies to positions with direct reports).
• 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director and above).

Principal Duties and Responsibilities:

• Leads others and independently determines circuit-level specifications based on system-level requirements.
• Uses technical expertise with advanced tools/applications to develop module-level architecture and design of multiple complex blocks based on specifications.
• Effectively utilizes advanced RFIC engineering practices to resolve complex architecture and design problems.
• Runs complex simulations to determine how circuits perform under various circumstances.
• Lead others to floor-plan layout; collaborates with layout engineers to generate the layout of circuits and conduct physical verification on the layout; perform review of generated layout.
• Reviews block-level test plans and reviews test results and provides instructions for test engineers; helps more junior team members do the same.
• Ensure that bugs are fully understood and analyzed; responsible for helping to resolve internal and end-customer issues.
• Seeks advanced knowledge of industry trends, previous generation's advances, competitors' products, and advances related to RFICs.
• Contributes to conversations to generate new ideas for next generation RFICs; provides recommendations for new directions to explore.
• Reviews and writes clear and detailed technical documentation and feature descriptions for complex projects to guide users; reviews and provides feedback on more junior engineers' documentation.

Level of Responsibility:

• Working under some supervision.
• Providing some supervision/guidance to others.
• Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct).
• Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area.
• Working within prescribed budget and resources.
• Having a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to provide input on key decisions).
• Completing most tasks with multiple steps which can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively; mistakes may result in some rework.
• Exercising creativity to draft original documents, imagery, or work products within established guidelines.
• Using deductive and inductive problem solving; multiple approaches may be taken/necessary to solve the problem; often information is missing or incomplete; intermediate data analysis/interpretation skills may be required.
• May be solicited during strategic planning period.

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Pay range and Other Compensation & Benefits:

$168,600.00 - $252,800.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.