DFM RET Engineer

118-WW TMG MFG OPS; Dallas (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Texas Instruments is seeking a DFM/OPC Engineer to advance 28nm and below photolithography capabilities within the Advanced Technology Development (ATD) organization. You will bridge design intent with fab printability, developing OPC models, DFM solutions, and automation that ensures reliable silicon realization.

The role sits at the intersection of computational lithography, layout design, and process integration, with opportunities to mentor junior engineers and influence cross-functional

Qualifications

• Master’s or Ph.D. in Electrical Engineering, Physics, Materials Science, or related field.
• 5+ years of hands-on OPC and DFM experience in the semiconductor industry.
• Strong understanding of optical lithography principles and RET (OPC, SRA, assist features, mask technology).
• Hands-on experience with industry-standard OPC tools (e.g., Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion).
• Familiarity with 28nm/22nm process constraints and lithographic limitations.
• Proficiency in scripting languages (Python, TCL, Perl, or equivalent).

Responsibilities

• Develop, evaluate, and implement advanced OPC models and recipes for 28nm and equivalent advanced node technologies.
• Perform comprehensive DFM analysis on product designs, identifying and mitigating potential manufacturing issues (e.g., hotspots, yield detractors).
• Collaborate with design teams to define DFM guidelines and ensure layout compliance with manufacturing capabilities.
• Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window.
• Interface with OPC and lithography engineers to co-optimize layout structures for printability.
• Analyze lithography process data and wafer yield data to identify root causes of patterning defects and drive corrective actions.
• Evaluate and qualify new OPC/DFM software tools and methodologies
• Develop and maintain automation scripts for OPC/DFM flows
• Contribute to DFM-aware layout methodologies for custom analog IPs
• Mentor junior engineers and contribute to team knowledge sharing

Skills

OPC/DFM engineering

Scripting

Analytical thinking

Education

Master’s or Ph.D. in EE, Physics, Materials Science, or related field

Tools

Synopsys Sentaurus Lithography

Siemens EDA Calibre

ASML Brion

Cadence Virtuoso

Job description

Change the world. Love your job.
Texas Instruments is in an exciting era of growth and innovation, and our Advanced Technology Development (ATD) organization is at the center of it. We are developing the 28nm process technologies that will define TI’s next generation of analog and embedded processing capabilities. As part of ATD, you won’t just support production, you’ll create the technology that makes it possible. Our engineers are working at the leading edge of computational lithography, Resolution Enhancement Techniques, and advanced process integration, solving the fundamental patterning and process challenges that determine whether a 28nm technology can be manufactured at scale and at yield. The work done in ATD directly enables fabs that will manufacture tens of millions of analog and embedded processing chips every day supporting customer demand for decades to come. We’re committed to responsible, sustainable semiconductor manufacturing and to building a diverse, technically excellent team that drives meaningful impact across the industry. In this role, you’ll work at the intersection of fundamental research and high-volume manufacturing, turning process innovations into production-ready technologies that power electronics everywhere.

Job Description:

At 28nm and below, photolithography cannot simply print a chip design as drawn but rather optical diffraction causes critical features to print incorrectly, with direct consequences to yield and device performance. Solving that problem is your job. As a DFM/OPC Engineer in TI’s Resolution Enhancement Techniques (RET) team within ATD, you are the technical authority responsible for bridging the gap between what designers draw and what the fab can reliably print. You’ll develop, optimize, and deploy Optical Proximity Correction (OPC) models and Design for Manufacturability (DFM) solutions that ensure every product tapeout can be accurately realized in silicon at 28nm at yield entitlement. This role sits at the intersection of computational lithography, layout design, and process integration; your work is a prerequisite for every analog product TI ships from LFAB.

Responsibilities:

• Develop, evaluate, and implement advanced OPC models and recipes for 28nm and equivalent advanced node technologies

• Perform comprehensive DFM analysis on product designs, identifying and mitigating potential manufacturing issues (e.g., hotspots, yield detractors)

• Collaborate with design teams to define DFM guidelines and ensure layout compliance with manufacturing capabilities

• Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window

• Interface with OPC and lithography engineers to co-optimize layout structures for printability

• Analyze lithography process data and wafer yield data to identify root causes of patterning defects and drive corrective actions

• Evaluate and qualify new OPC/DFM software tools and methodologies

• Develop and maintain automation scripts for OPC/DFM flows

• Contribute to DFM-aware layout methodologies for custom analog IPs

• Mentor junior engineers and contribute to team knowledge sharing

Minimum Requirements:

• Master’s or Ph.D. in Electrical Engineering, Physics, Materials Science, or related field

• 5+ years of hands-on OPC and DFM experience in the semiconductor industry

• Strong understanding of optical lithography principles and RET (OPC, SRA, assist features, mask technology)

• Hands-on experience with industry-standard OPC tools (e.g., Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion)

• Familiarity with 28nm/22nm process constraints and lithographic limitations

• Proficiency in scripting languages (Python, TCL, Perl, or equivalent)

Preferred Qualifications:

• Experience with analog layout interaction with lithography and OPC flows

• Familiarity with layout tools (e.g., Cadence Virtuoso); knowledge of DRC and LVS

• Experience applying machine learning or AI techniques to OPC/DFM problems

• Strong cross-functional collaboration and analytical skills