PD-CAD Engineer

Socket.dev; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Job summary

Apple is seeking a Hardware CAD engineer to join the Silicon Technologies group in Austin, TX. You will help design and implement flows, tools, and methodologies for high-performance, power-efficient SoCs, collaborating with design teams to improve PPA and productivity.

You will work with EDA vendors, develop internal CAD solutions, and enable deployment of new tech nodes, stdcells, and ML-based optimization, contributing to world-class chips used in Apple devices.

Qualifications

• Minimum BS in a technical field.
• Experience with CAD flow or PD methodology is preferred.
• Familiarity with PNR tools and ASIC physical design.

Responsibilities

• Participating or leading cross functional teams to tackle key physical design challenges.
• Developing innovative solutions in physical design and optimization space.
• Developing and supporting implementation flows for multiple projects and design teams.
• Developing and maintaining custom CAD tools for implementation and signoff.
• Creating flows to enable deployment of new technology nodes.
• Developing tools and methodologies for PPA and productivity including ML-based solutions.
• Collaborating with other teams such as physical design verification, RC extraction, STA.
• Working directly with EDA tool vendors to resolve tool issues and identify areas for tool improvements.

Skills

CAD flow

PD methodology

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Tcl

Python

Perl

PNR tools

Job description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As part of the Hardware Technology CAD team, you’ll help design our next-generation, high-performance, power-efficient SoCs. You will work on world class CPU, GPU, Analog/Mixed Signal and SOC designs by developing flows, tools and methodologies for future Apple products! You will explore and enable new technology nodes, stdcells and tools for design teams. You will collaborate with design teams and tool vendors to improve PPA (Power, Performance, Area) and design productivity. You will actively work on developing internal methodologies using your understanding of CAD algorithms and ML. We are looking for passionate engineers to join our team. In this role, you will be impacting a wide range of chips used across Apple’s world-class products.

Description

• Participating or leading cross functional teams to tackle key physical design challenges.
• Developing innovative solutions in physical design and optimization space.
• Developing and supporting implementation flows for multiple projects and design teams.
• Developing and maintaining custom CAD tools for implementation and signoff.
• Creating flows to enable successful deployment of new technology nodes.
• Developing tools and methodologies for best-in-class PPA and productivity including ML based solutions.
• Collaborating with other teams such as physical design verification, RC extraction, IR and static timing analysis (STA).
• Working directly with EDA tool vendors to resolve tool issues and identify areas for tool improvements.

Minimum Qualifications

• Minimum BS

Preferred Qualifications

• Experience in CAD flow or PD methodology development.
• Proficiency with Tcl, Python or Perl scripting languages.
• Hands on knowledge of industry standard PNR tools.
• Understanding and experience in analysis aspects of Physical Design - extraction, timing, noise, physical verification, EMIR.
• Hands on experience with high performance and low power implementation flows.