PCB Layout Engineer

Yochana; Menlo Park (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Yochana is seeking an experienced PCB Layout Engineer to own end-to-end PCB layouts for data center server boards. You will perform high-speed digital layouts for interfaces such as HBM, DDR5/LPDDR5, PCIe Gen5/6, and USB, ensuring controlled impedance and tight length matching.

You will enforce design rules across high-density boards and collaborate with EE and ME teams. The role demands deep HDI via experience and proficiency with Cadence Allegro, plus CES constraint-driven design knowledge.

Qualifications

• Advanced proficiency in Allegro PCB for layout and design.
• Strong knowledge of CAD software for 2D/3D design.
• 10-14 years CAD experience; Cadence Allegro Layout tool 23.1+ mandatory.
• Hands-on experience in HDI micro via technology.
• Intel or complex SoC/FPGA based PCB design experience preferred.
• Ability to deliver PCB CAD layout of High Density, High Speed memory designs (DDR5/LPDDR5), PCIe Gen5/6, Power Delivery.
• Deep knowledge of CES and high-speed constraint driven designs; DFA/DFM/DFT knowledge.
• Strong communication and presentation abilities.

Responsibilities

• Own end-to-end PCB layout for complex, high-density designs used in data center server boards.
• Perform high-speed digital layout for interfaces like HBM, DDR4/5, PCIe Gen 5/6, USB 3.2+.
• Develop and enforce layout design rules for various domains within wearable form factors.
• Collaborate with electrical engineers to review schematics and provide layout-driven feedback.
• Partner with mechanical engineers on board outline, connector placement, thermal management.
• Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators.
• Maintain and improve PCB design standards, layer stack-up libraries, footprint libraries.
• Support layout documentation, net tracing, and design revision analysis for protos/production.

Skills

Allegro PCB

CAD software

HDI via

High-density layout

High-speed design

Memory/DDR5 PCIe

Power delivery

DFM/DFT

Communication skills

Education

CAD experience 10-14 years

Tools

Cadence Allegro Layout

2D/3D CAD tools

CES (Constraint Editor)

Job description

Must have : Allegro PCB and CAD Software

Key Responsibilities

• Own end-to-end PCB layout for complex, high-density designs used in data center server boards
• Perform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigation
• Develop and enforce layout design rules for High-speed digital, analog, mixed-signal, and power domains within tightly constrained wearable form factors
• Collaborate with electrical engineers to review schematics and provide layout-driven feedback on component placement, power distribution network design, and signal routing strategies
• Partner with mechanical engineers to resolve physical constraints including board outline, connector placement, thermal management, and stack-up definition
• Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure layouts meet yield and reliability targets
• Maintain and improve PCB design standards, layer stack-up libraries, and footprint libraries to support scalable development across multiple hardware programs
• Support by providing layout documentation, net tracing support, and design revision analysis for prototype and production boards

Skill Requirements

• Advanced Proficiency In Allegro Pcb For Pcb Layout And Design.
• Strong Knowledge Of Cad Software For 2D And 3D Design Applications.
• 10-14 years of CAD experience, Cadence Allegro Layout tool 23.1 and above experience is mandatory
• Hands on experience in HDI micro via( Blind/Buried) technology
• Intel or high complex SoC/Microprocessor/FPGA based PCB design experience preferred
• High complex SoC/Microprocessor/FPGA based PCB design experience preferred
• Ability to deliver PCB CAD layout of High Density, High Speed memory designs (DDR5/LPDDR5), PCIe Gen 5 or Gen 6, Power Delivery, Mixed Analog/Digital
• Deep knowledge of CES (Constraint Editor) and high -speed constraint driven designs, DFA/DFM/DFT knowledge to adhere to Quality PCB fabrication and assembly assurance

Strong Communication And Presentation Abilities To Effectively Convey Design Concepts