Package Layout Engineer

Acceler8 Talent; California; On-site; USD 130,000 - 180,000; Full time

Benefits offered by this job

401(k)

Dental insurance

Vision insurance

Medical insurance

Job summary

Acceler8 Talent in Mountain View, CA seeks a Package Layout Engineer to own the physical design of advanced semiconductor packages for AI accelerators, leading end-to-end substrate and interposer layouts from stackup definition to tapeout, in collaboration with silicon, SI/PI, and PCB teams.

Responsibilities include bump mapping, 2.5D/3D integration, high-density RDL routing, power/ground networks, and OSAT coordination to meet manufacturing requirements.

Qualifications

• 8+ years of semiconductor package layout experience.
• Expertise in 2.5D/3D packaging and multi-die integration techs (CoWoS, EMIB, InFO etc).
• Experience with package substrate/interposer layout and high-density routing.

Responsibilities

• Own end-to-end package substrate and interposer layout, including stackup, bump map planning, RDL routing, and final design release.
• Design multi-die 2.5D/3D packages for high-bandwidth memory interfaces and accelerators.
• Develop package power and ground distribution networks for high-current requirements.
• Collaborate with silicon, SI/PI, PCB teams, and OSAT partners to meet manufacturing needs.
• Perform package DRC/LVS and netlist verification.
• Resolve routing, SI/PI, and manufacturability challenges.
• Develop AI-assisted design tools to accelerate layout and verification.

Skills

Package layout

2.5D/3D packaging

RDL design

Power/ground integrity

Cross‑functional collaboration

High-density routing

Tools

Cadence Allegro Package Designer

Cadence SiP Layout

Siemens Xpedition Package Designer

Job description

Package Layout Engineer

Location: Mountain View, CA

Onsite

About the Role

An innovative AI hardware startup is seeking an experienced Package Layout Engineer to own the physical design and development of advanced semiconductor packages for next-generation AI accelerators.

This role offers end-to-end ownership of complex 2.5D and 3D multi-die package layouts, from initial bump mapping and stackup definition through substrate routing, interposer design, verification, and tapeout release.

You'll work closely with silicon physical design, signal and power integrity, PCB layout, and packaging teams to develop high-performance packages supporting advanced AI computing systems.

Key Responsibilities

• Own end-to-end package substrate and interposer layout, including stackup definition, bump and ball map planning, redistribution layer (RDL) routing, high-density escape routing, and final design release.
• Design and optimize multi-die 2.5D/3D packages supporting high-bandwidth memory (HBM) interfaces and high-performance accelerator silicon.
• Develop package power and ground distribution networks capable of supporting high-current accelerator requirements.
• Drive die-to-package-to-board co-design, collaborating with physical design teams on bump placement and floorplanning and PCB teams on board-level interfaces.
• Perform package design rule checking (DRC), layout-versus-schematic (LVS), and netlist verification.
• Collaborate with outsourced semiconductor assembly and test (OSAT) partners and substrate suppliers to ensure designs meet manufacturing requirements.
• Resolve complex package routing, signal integrity, power integrity, and manufacturability challenges.
• Develop and leverage AI-assisted design tools to accelerate package layout, routing optimization, and signoff processes.

Required Qualifications

• 8+ years of professional semiconductor package layout experience, ideally involving high-performance computing, AI accelerators, GPUs, or other advanced semiconductor systems.
• Strong expertise in advanced 2.5D/3D packaging and multi-die integration technologies, such as CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies.
• Hands‑on experience with package substrate and interposer layout, high-density escape routing, and RDL design.
• Deep understanding of package stackup architecture, bump and ball mapping, via structures, and high‑current power/ground plane design.
• Proficiency with industry‑standard package layout tools such as Cadence Allegro Package Designer, Cadence SiP Layout, Siemens Xpedition Package Designer, or equivalent.
• Experience with package DRC/LVS verification, design rule management, and manufacturing signoff.
• Demonstrated ability to collaborate with silicon architecture, physical design, SI/PI, thermo‑mechanical engineering, and OSAT partners to complete complex package designs.

Preferred Qualifications

• Experience designing advanced packages for AI accelerators, GPUs, or high‑performance processors.
• Familiarity with HBM integration, chiplet architectures, and heterogeneous multi‑die systems.
• Experience with die‑to‑package‑to‑board co‑design and package‑level signal/power integrity optimization.
• Background working directly with semiconductor substrate suppliers and OSAT partners.
• Experience developing automation scripts or AI‑assisted workflows for package layout, routing, and verification.

Final compensation will depend on experience, technical expertise, and role level.

The employer welcomes qualified candidates requiring employment‑based visa sponsorship or transfer, including eligible H-1B, O-1, TN, E-3, F-1 OPT, and STEM OPT candidates, subject to applicable requirements.

Certain responsibilities may involve technologies subject to U.S. export control regulations (EAR/ITAR).

The employer is committed to equal employment opportunities and providing reasonable accommodations throughout the hiring process.

Featured benefits

• 401(k)
• Dental insurance
• Vision insurance
• Medical insurance