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Texas Instruments Incorporated is seeking a Senior OPC Technology Transfer Engineer to bridge R&D and High-Volume Manufacturing—owning the full transfer lifecycle.
You will analyze process disparities, partner with Fab staff, and drive test-wafer programs while leveraging large datasets and CD-SEM data to verify model behavior against production silicon.
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. Put your talent to work with us – change the world, love your job!
As a Senior OPC Technology Transfer Engineer within the Advanced Technology Development (ATD) organization, you will bridge the gap between initial R&D development and High-Volume Manufacturing (HVM) by owning the full lifecycle of transferring developed OPC technologies to production Fabs. In this role, you will thoroughly analyze process, equipment, layout, and tool disparities between R&D and HVM environments to proactively predict, mitigate, and resolve transfer risks prior to recipe release, ensuring a seamless, high-yield production ramp-up. You will utilize your deep technical knowledge of core semiconductor processes—specifically Photolithography and Etching—to align transferred OPC solutions with production-line physics and hardware characteristics. Serving as a technical leader crossing organizational boundaries, you will partner closely with manufacturing operators, shift technicians, and Fab staff to coordinate test wafer execution, align expectations, and drive collaborative alignment. Additionally, you will leverage data science methodologies to collect, analyze, and interpret large-scale wafer measurement datasets to evaluate OPC recipe performance for final manufacturing sign-off, while compiling and analyzing high-volume SEM images and Critical Dimension (CD) data to verify R&D software model behavior against physical production silicon. Finally, you will analyze automated OPC verification results to identify lithographic critical care-abouts and strategically select key metrology targets for systematic layout review and CD-SEM measurement tracking.