Onsite RTL IC Design Engineer — Data Center AI/ML, Equity & Bonus

Broadcom; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Discretionary bonus

Equity awards and ESPP

Job summary

Broadcom is seeking a Digital IC Design Engineer in the Data Center Solutions Group in San Jose, CA. You will implement RTL in Verilog/SystemVerilog, drive timing closure, and collaborate with cross-functional teams to support PCIe Switch products and AI/ML data center workloads.

The role emphasizes in-depth RTL design, debugging, and architecture analysis, with mandatory on-site work in San Jose. A bachelor’s degree and 5+ years of experience are required.

Qualifications

• Bachelor's degree required in Electrical/Electronic/Computer Eng.
• 5+ years of relevant industry experience.
• Must work in person in San Jose, CA – no remote work.

Responsibilities

• High-level architecture specification analysis and reviews.
• Micro-architecture development and documentation.
• RTL implementation in Verilog/SystemVerilog focusing on timing closure.
• RTL debugging with robust solutions.
• Collaborate with Verification, Software/Firmware, Emulation, and Validation teams.
• Lab support for silicon validation.

Skills

Verilog

SystemVerilog

RTL design

Timing closure

Debug RTL

PCIe

Collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

Verilog/SystemVerilog

Job description

Broadcom is seeking a Digital IC Design Engineer in the Data Center Solutions Group in San Jose, CA. You will implement RTL in Verilog/SystemVerilog, drive timing closure, and collaborate with cross-functional teams to support PCIe Switch products and AI/ML data center workloads.

The role emphasizes in-depth RTL design, debugging, and architecture analysis, with mandatory on-site work in San Jose. A bachelor’s degree and 5+ years of experience are required.