Onsite FPGA Engineer II - Powering Critical Defense Systems

globalhr; Fort Wayne (IN); On-site; USD 69,000 - 131,000; Full time

Job summary

RTX in Fort Wayne, IN is seeking an FPGA Engineer II to design and verify FPGA-based sensor and processor systems onsite. You will work with multidisciplinary teams to define requirements, develop architectures, perform detailed design, simulations, integration, and verification throughout the lifecycle.

The role requires an active DoD Secret clearance or the ability to obtain one, and a strong foundation in FPGA/ASIC design with experience in VHDL/Verilog.

Qualifications

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 2 years of prior relevant experience.
• Experience with FPGA/ASIC design or verification (VHDL/Verilog) and with tools such as Vivado/Quartus/Libero.
• Hands-on experience with integration and debugging of FPGA/ASIC in a lab environment.
• Experience with source code management, design reviews, and code release in a team development environment.

Responsibilities

• Provide full lifecycle support of production quality FPGA designs for major vendors and device families (AMD Xilinx, Altera, Microchip).
• Generate FPGA designs for gigabit interfaces, RF DSP, controls, data links, embedded processing.
• Assist with architecture development of FPGA-based systems and CONOPS.
• Design and code in VHDL/Verilog for reliability and maintainability.
• Support design verification with self-checking tests and coverage tracking.

Skills

FPGA Design

Verilog/VHDL

Lab Debugging

Source Control

Design Reviews

Education

B.S. in STEM

M.S. in Electrical Engineering

Tools

Vivado

Quartus Prime Pro

Libero

Job description

RTX in Fort Wayne, IN is seeking an FPGA Engineer II to design and verify FPGA-based sensor and processor systems onsite. You will work with multidisciplinary teams to define requirements, develop architectures, perform detailed design, simulations, integration, and verification throughout the lifecycle.

The role requires an active DoD Secret clearance or the ability to obtain one, and a strong foundation in FPGA/ASIC design with experience in VHDL/Verilog.