NPU Architect for Next-Gen SoCs — HW/SW Co-Design Lead

Samsungresearchamerica

Mountain View (CA)

On-site

USD 243,000 - 377,000

Full time

14 days+
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Job summary

Samsung Research America is seeking an experienced NPU Architect to lead architecture and micro-architecture work for next-generation SOCs, focusing on NPU sub-systems, interfaces and power-performance tradeoffs.

You will drive early-stage exploration, machine learning research, feature definitions, performance modeling, and hardware-software co-optimization, collaborating across hardware and software teams to deliver silicon-ready solutions.

Responsibilities

  • Propose innovative NPU Architectural and micro-architectural features to boost PPA on various targeted workloads in next generation SOCs
  • Perform high-level performance modeling/simulation and analysis of NPU features, applications, benchmarks, and complex uses case
  • Develop cycle accurate and analytical NPU performance model and correlate with Silicon
  • Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
  • Analyzing benchmarks, application workloads, and performance simulation results for architecture and microarchitecture optimizations
  • Map AI use cases to NPU.
  • Optimize and co-design of SW and HW to develop new architectures for low power and high performance
  • Collaborate across teams to bring architecture proposals to fruition across the SOC, Driver, OS and System through detailed documentation

Job description

Samsung Research America is seeking an experienced NPU Architect to lead architecture and micro-architecture work for next-generation SOCs, focusing on NPU sub-systems, interfaces and power-performance tradeoffs.

You will drive early-stage exploration, machine learning research, feature definitions, performance modeling, and hardware-software co-optimization, collaborating across hardware and software teams to deliver silicon-ready solutions.

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