NoC Interconnect Design Engineer and Architect

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Competitive annual discretionary bonus program

Opportunity for annual RSU grants

Comprehensive benefits package

Job summary

Qualcomm in San Diego is seeking an experienced candidate for a role in Engineering Group focused on ASIC design. The position involves creating micro-architecture specifications, analyzing performance results, and driving new protocol deployments.

Qualified candidates should demonstrate strong knowledge of bus protocols, ASIC flow, and must possess excellent problem-solving skills. A Bachelor's or higher degree in Science or Engineering and relevant experience are required for this role.

Qualifications

• 2+ years of ASIC design, verification, validation, integration, or related work experience.
• 1+ year of ASIC design, verification, validation, integration, or related work experience for Master's holders.

Responsibilities

• Create micro-architecture bus component specifications and analyze performance results.
• Deliver RTL and run tool flows for new protocol deployments.
• Support verification and silicon validation teams.

Skills

Knowledge of various bus protocols (AHB, AXI, CHI)

Architecture tradeoff analysis

ASIC flow knowledge (synthesis, STA, Lint)

Troubleshooting and problem solving skills

Micro-architecture performance/power/area tradeoff

Excellent communication skills

Familiarity with CPU architecture

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Job description

Company: Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

The NoC bus team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery to the SoCs. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect.

Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.

Responsibilities:

The successful applicant will be responsible for creating micro-architecture bus components specifications as well as analyzing the performance results, deliver RTL and run tool flows. Responsibilities also include evaluating new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC. Candidate should also be able to deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the interconnects.

Skills/Experience:

• Knowledge of various bus protocols (AHB, AXI, CHI, …), network on chip.
• Strong working knowledge of architecture tradeoff analysis.
• Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools.
• Skills for troubleshooting and problem solving, including RTL design, FPGA and post-silicon debug.
• Ability to define bus components micro-architecture with knowledge of performance/power/area tradeoff.
• Ability to quickly react and adapt to changes.
• Excellent communication skills.
• Familiarity with CPU architecture is a big plus.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Pay Range and Other Compensation & Benefits:

$115,600.00 - $173,400.00. The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits.

EEO Statement:

Qualcomm is an equal opportunity employer. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.

If you would like more information about this role, please contact Qualcomm Careers.