New Graduate Engineer, Silicon Engineering

United States Digital Space LLC; Irvine (CA); On-site; USD 125,000 - 195,000; Full time

Benefits offered by this job

Stock options

Performance bonuses

Medical, vision, dental coverage

Job summary

United States Digital Space LLC is seeking a New Graduate Engineer for Silicon Engineering to join the Starlink program. You will work on ASIC/FPGA design, RTL and verification, and lab bring-up with embedded software in C/C++ and Python, across multiple disciplines.

The role offers full-time employment in Palo Alto, Irvine (CA), or Redmond (WA) with exposure to RFIC/analog design, DSP, and physical implementation in advanced tech nodes.

Qualifications

• Graduating with a bachelor’s, master’s, or PhD in 2026 or 2027.
• Bachelor’s degree in engineering, mathematics or physics required.
• Experience with ASIC, SOC, FPGA, RFIC, or MMIC.

Responsibilities

• Participate in all phases of ASIC/FPGA design and verification.
• Contribute towards RTL implementation and verification; emulation.
• Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python).
• Develop RF/microwave circuits and perform floor planning and layout.

Skills

SystemVerilog/Verilog/VHDL

C/C++ programming

Digital signal processing

Python scripting

RF/Analog design basics

Computer architecture

Education

Bachelor’s degree in engineering / mathematics / physics

Master’s or PhD in related field (preferred)

Tools

ADS

Spectre

HFSS

Momentum

Job description

the company was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today the company is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

NEW GRADUATE ENGINEER, SILICON ENGINEERING

Are you an engineering student graduating in fall or this upcoming spring/summer that is looking for full-time employment after graduation? We are looking for engineers to help us develop next generation silicon for the company. The team is hiring engineers from pre-silicon through post-silicon across many disciplines in RF/Analog IC, RTL design, design verification, physical design, DFT, validation and more using state-of-the-art tools and methodologies. The ideal candidate will be a hands-on self-starter who can execute the steps required to fully design and verify complex designs.

Full-time employment is available working on our Starlink program in Palo Alto (CA), Irvine (CA), or Redmond (WA).

RESPONSIBILITIES:

• ASIC/FPGA Design & Verification
  • Participate in all phases of ASIC/FPGA design and verification flows
  • Contribute towards design architecture, RTL implementation and/or verification, and emulation
  • Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python)
  • Hands-on self-starter who can execute the steps required to fully verify a complex digital design
• RF/Analog IC Design
  • Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains
  • Derive specifications for the RFIC subsystems and circuits
  • Develop RF/microwave circuits in state-of-the-art SiGe or CMOS processes
  • Perform IC floor planning and layout
• Digital Signal Processing
  • Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)
  • Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers
• Physical Design
  • Perform synthesis and physical implementation steps (synthesis, floor planning, place and route, timing/noise analysis, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Participate in silicon tapeouts in advanced technology nodes for future Starlink SOCs

BASIC QUALIFICATIONS:

• Graduating with a bachelor’s degree, master’s degree or PhD in 2026 or 2027
• Bachelor’s degree in an engineering discipline, mathematics or physics
• Experience working with ASIC, SOC, FPGA, RFIC, or MMIC

PREFERRED SKILLS AND EXPERIENCE:

• Understanding of computer architecture
• Experience in one or more of the following areas:
  • Analog or digital CMOS integrated circuit design and/or physical design
  • SystemVerilog, Verilog, VHDL or C/C++
  • Scripting languages, e.g. Python for automation
  • Object-oriented programming
  • Simulation tools such as ADS, Spectre, HFSS or Momentum
  • RTL design, chip bring-up, verification, and/or post-silicon validation experience
  • Digital signal processing

ADDITIONAL REQUIREMENTS:

• Ability to work extended hours and weekends as necessary to meet critical project milestones

COMPENSATION AND BENEFITS:

Pay Range:
Level 1: $125,000.00 - $160,000.00
Level 2: $145,000.00 - $195,000.00

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at the company. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s Affemative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].