Neuromorphic ASIC Design Automation Engineer (Hybrid)

Intel; Hillsboro (OR); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Job summary

Intel is seeking an experienced design automation engineer to push the boundaries of neuromorphic silicon at Loihi. You will shape tool flows across front-end design, physical implementation, verification, and FPGA emulation, collaborating with RTL, QA, and physical teams to drive innovation.

Applicants should bring a strong software background, familiarity with asynchronous design, and a willingness to learn AI-driven automation.

Qualifications

• Bachelors and 4+ years OR Masters and 2+ years of experience in developing and deploying production quality tools for silicon design.
• 4+ years of experience in developing and maintaining the entire ASIC tool suite (synthesis, place and route, ATPG, FEV, RV, STA, LVS/DRC).
• 4+ years of experience with scripting languages such as Perl, TCL, Python, etc.
• 2+ years of experience in delivering multiple silicon tape-outs.

Responsibilities

• Enhance and maintain Loihi's asynchronous EDA tool flow by implementing design automation algorithms, software tools, utilities, and regression tests.
• Support RTL designers, verification engineers and physical design engineers by providing automated solutions to achieve product quality and target KPIs.
• Enable early SW development by setting up a scalable framework mapping silicon designs in simulation and emulation.
• Write custom scripts to manipulate synthesis and physical design tools for low power/high performance designs.

Skills

Python

Perl

TCL

SystemVerilog

Education

Bachelor's degree in Electrical Engineering or Computer Science

Master's degree in Electrical Engineering or Computer Science

Tools

Synthesis tools

Place & Route tools

ATPG

FEV

RV

LVS/DRC

Python scripting

Job description

Intel is seeking an experienced design automation engineer to push the boundaries of neuromorphic silicon at Loihi. You will shape tool flows across front-end design, physical implementation, verification, and FPGA emulation, collaborating with RTL, QA, and physical teams to drive innovation.

Applicants should bring a strong software background, familiarity with asynchronous design, and a willingness to learn AI-driven automation.