NAND Quality and Reliability RD Engineer

Solidigm; San Jose (CA); Hybride; USD 140 000 - 255 000; Plein temps

Avantages offerts par ce poste

RSU eligibility

Restricted cash unit eligibility

Cash bonus programs

Medical, dental, vision benefits

401(k) company match

Résumé du poste

Solidigm is seeking a semiconductor memory engineer to design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability.

You will develop and optimize trims to minimize program and read disturb, and to optimize performance and power, without compromising reliability. Collaboration with Device, Design, Reliability, and Product/Test teams is key to advancing SSD technology.

Qualifications

• Bachelor’s in electrical engineering, microelectronics, or a closely related field.
• 2+ years of industry experience in semiconductor memory technologies and products.
• Deep understanding of NAND cell and array operations, including array reliability physical mechanisms and characterization techniques.
• Strong foundation in semiconductor device physics and process flows.
• Proficiency in statistical analysis methodologies and tools.
• Hands-on programming experience in C, C++, Python, and/or JMP.
• Proven ability to thrive in a fast-paced, cross-functional team environment.
• Strong analytical and problem-solving skills with attention to detail.
• Excellent communication and presentation skills, with the ability to convey complex technical concepts to diverse audiences.

Responsabilités

• Design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability.
• Develop and optimize trims to minimize program and read disturb, directly impacting product quality.
• Develop and optimize trims to optimize performance and power (tPROGRAM, tREAD, Icc), without impacting reliability and endurance capabilities.
• Apply NAND device physics principles to explain and interpret relationships between experimental data and trim parameters.
• Conduct comprehensive data analysis to identify and communicate trade-offs across multiple parameters of interest.
• Use NAND device physics knowledge and problem-solving skills to design experiments, identify product failure mechanisms, and implement effective solutions.
• Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams to design, test, and deeply innovative method to improve performance and reliability.

Connaissances

C/C++

Python

JMP

Statistical analysis

Communication

Formation

Bachelor’s in Electrical Engineering or Microelectronics

Master’s or PhD (preferred)

Outils

JMP

Description du poste

Job Description

NAND array algorithm development and performance/reliability engineering.

Key Responsibilities:

• Design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability.
• Develop and optimize trims to minimize program and read disturb, directly impacting product quality.
• Develop and optimize trims to optimize performance and power (tPROGRAM, tREAD, Icc), without impacting reliability and endurance capabilities.
• Apply NAND device physics principles to explain and interpret relationships between experimental data and trim parameters.
• Conduct comprehensive data analysis to identify and communicate trade-offs across multiple parameters of interest.
• Use NAND device physics knowledge and problem-solving skills to design experiments, identify product failure mechanisms, and implement effective solutions.
• Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams to design, test, and deeply innovative method to improve performance and reliability.

Qualifications:

Qualifications

Required Qualifications:

• Bachelor’s in electrical engineering, Microelectronics, or a closely related field.
• 2+ years of industry experience in semiconductor memory technologies and products.
• Deep understanding of NAND cell and array operations, including array reliability physical mechanisms and characterization techniques.
• Strong foundation in semiconductor device physics and process flows.
• Proficiency in statistical analysis methodologies and tools.
• Hands-on programming experience in C, C++, Python, and/or JMP.
• Proven ability to thrive in a fast-paced, cross-functional team environment.
• Strong analytical and problem-solving skills with attention to detail.
• Excellent communication and presentation skills, with the ability to convey complex technical concepts to diverse audiences.

Preferred Qualifications:

• Master's or PhD in Electrical Engineering, Microelectronics, or a closely related field.
• Experience with 3D NAND architecture and advanced memory scaling challenges.
• Experience in SSD system level FW design and testing

Additional Information

This position is also eligible to participate in Solidigm's restricted stock unit (RSU), restricted cash unit (RCU), and cash bonus programs. In addition, Solidigm offers a benefits package that includes medical, dental, vision, supplemental life and AD&D insurance; short- and long-term disability; healthcare and dependent care flexible spending accounts, and a company match on eligible 401(k) plan contributions.

The compensation range for this role is $139,520 - $255,000. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location.

Working Conditions:

Rancho Cordova CA or San Jose CA ; Full-time hybrid; at least 3 days per week onsite.

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Compensation:

$139,520-$139,520 per year