ML Platform Architect - Silicon & SoC Systems

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 216,000 - 325,000; Full time

Benefits offered by this job

Stock programs

Relocation eligibility

Educational reimbursement

Job summary

Apple Inc. is seeking a senior role within the Platform Architecture group in Cupertino to map ML workloads onto Apple silicon and develop performance models.

The candidate will evaluate optimization techniques and influence hardware and algorithm directions while collaborating with ML, system, and IP teams. Responsibilities include implementing ML workloads on Neural Engine, GPU, and CPU; developing high-level models; and analyzing trade-offs to guide future hardware design.

Qualifications

• Experience in C/C++ and/or Python.
• Experience with ML frameworks and efficient ML algorithm implementations.
• Experience with hardware IPs: ML HW accelerators, GPU/CPU, image/video processors or similar.

Responsibilities

• Create optimized implementations of ML workloads on Apple silicon including Neural Engine, GPU, and CPU.
• Collaborate with IP and SoC architecture teams to develop performance models and simulations of future hardware.
• Collaborate with system teams to create high-level performance models of emerging ML techniques and analyze system architecture trade-offs.
• Evaluate emerging ML model optimization techniques through experimentation and analysis; propose new ideas to inform hardware and algorithm direction.

Skills

C/C++

Python

ML frameworks

Education

MS or PhD in EE/CE/CS

Tools

PyTorch

Job description

Apple Inc. is seeking a senior role within the Platform Architecture group in Cupertino to map ML workloads onto Apple silicon and develop performance models.

The candidate will evaluate optimization techniques and influence hardware and algorithm directions while collaborating with ML, system, and IP teams. Responsibilities include implementing ML workloads on Neural Engine, GPU, and CPU; developing high-level models; and analyzing trade-offs to guide future hardware design.