ML Hardware Verification Manager

Meta; Sunnyvale (CA); On-site; USD 220,000 - 340,000; Full time

Job summary

Meta is seeking an experienced ML Hardware Verification Manager to lead verification of custom ML accelerators and silicon platforms for Reality Labs. You will supervise a team of hardware verification engineers, set verification strategy, and drive tape-out milestones with ML researchers, RTL designers, and software teams.

You will ensure functional correctness, coverage closure, and silicon readiness across tensor processors, memory subsystems, and interconnect fabrics, while aligning with

Qualifications

• 12+ years of experience in hardware design verification, including functional simulation, coverage-driven verification, and formal verification of digital logic.
• 5+ years of experience in managing hardware engineering teams, including setting technical direction and driving execution across multiple concurrent projects.
• Experience in Machine Learning on IPs and Silicon development.
• Knowledge of SystemVerilog Assertions, X-propagation, UPF-power aware, gate-level simulations.
• Experience with UVM-based testbench architecture and constrained-random verification methodologies applied to complex SoC or accelerator designs.
• Experience in driving verification closure for tape-out on custom silicon, including coverage analysis, regression management, and sign-off processes.
• Experience collaborating with RTL design, physical design, and post-silicon validation teams across the full silicon development lifecycle.
• BS degree in Electrical Engineering, Computer Science, or relevant field.
• Knowledge of convolutional neural networks, transformers, LLMs.
• Master's or PhD degree in Electrical Engineering, Computer Science, or relevant field.
• Familiarity with emulation platforms and FPGA-based prototyping as part of a pre-silicon verification flow.
• Experience with SW/HW co-design, firmware/HW interaction testing.
• Experience in verifying ML accelerator hardware components such as matrix multiply units, dataflow engines, or high-bandwidth memory interfaces.

Responsibilities

• Lead design verification for ML accelerators and silicon platforms.
• Manage a team of hardware verification engineers and drive functional correctness and coverage closure.
• Drive tape-out milestones and ensure silicon readiness across projects.
• Collaborate with ML researchers, RTL designers, physical designers, and software teams to define verification strategies.
• Define verification plans and ensure sign-off across pre- and post-silicon validation stages.

Skills

Hardware verification

Team management

ML IPs

SystemVerilog assertions

UVM testbench

Formal verification

Coverage analysis

Tape-out readiness

Cross-team collaboration

FW/HW co-design

Education

BS Electrical Engineering/CS

MS/PhD in EE/CS

Tools

UVM testbench

SystemVerilog

UPF-power

Gate-level sims

Emulation platforms

FPGA prototyping

Constrained-random

Python scripting

Job description

Meta is building custom silicon to power the next generation of AI and machine learning workloads across its Reality Labs products. We are seeking an experienced ML Hardware Verification Manager to lead the design verification efforts for custom ML accelerators and silicon platforms. In this role, you will manage a team of hardware verification engineers responsible for ensuring the functional correctness, coverage closure, and silicon readiness of ML-specific hardware designs, including tensor processing units, memory subsystems, and interconnect fabrics. You will partner closely with ML researchers, architects, RTL designers, and software teams to define verification strategies and drive tape-out milestones.

Qualifications and Experience

• 12+ years of experience in hardware design verification, including functional simulation, coverage-driven verification, and formal verification of digital logic
• 5+ years of experience in managing hardware engineering teams, including setting technical direction and driving execution across multiple concurrent projects
• Experience in Machine Learning on IPs and Silicon development
• Knowledge of SystemVerilog Assertions, X-propagation, UPF-power aware, gate-level simulations
• Experience with UVM-based testbench architecture and constrained-random verification methodologies applied to complex SoC or accelerator designs
• Experience in driving verification closure for tape-out on custom silicon, including coverage analysis, regression management, and sign-off processes
• Experience collaborating with RTL design, physical design, and post-silicon validation teams across the full silicon development lifecycle
• BS degree in Electrical Engineering, Computer Science, or relevant field
• Knowledge of convolutional neural networks, transformers, LLMs
• Master's or PhD degree in Electrical Engineering, Computer Science, or relevant field
• Familiarity with emulation platforms and FPGA-based prototyping as part of a pre-silicon verification flow
• Experience with SW/HW co-design, firmware/HW interaction testing
• Experience in verifying ML accelerator hardware components such as matrix multiply units, dataflow engines, or high-bandwidth memory interfaces