ML Hardware Engineer - Low-Latency FPGA/ASIC Architect

Fintal Partners; Chicago (IL); On-site; USD 140,000 - 230,000; Full time

Job summary

Fintal Partners in Chicago is seeking researchers and engineers to architect ML models co-designed with traders and software teams, accounting for latency budgets and hardware constraints. You will help shape our custom hardware roadmap and collaborate with hardware engineers from concept to production.

The role blends ML, hardware, and software, requiring understanding of neural networks, quantization, and inference optimization.

Qualifications

• Solid understanding of hardware constraints and design trade-offs when mapping ML models to FPGA/ASICs.
• Experience with HDL, HLS, or ML-to-hardware frameworks such as hls4ml, FINN, or Vitis AI.
• Foundations in machine learning: neural networks, inference optimization, quantization with PyTorch/TensorFlow.
• Proficiency in Python, C++, or similar languages for tooling, testing, and simulation.

Responsibilities

• Architect and co-design ML models with traders, quant researchers, and software engineers, treating hardware constraints as first-class inputs.
• Shape our custom hardware roadmap by translating ML model requirements into architectural decisions.
• Work hands-on with hardware engineers to implement, verify, and deploy ML inference solutions from proof-of-concept to production.
• Track and evaluate emerging research in neural architecture search, ML systems, and quantization, translating findings into measurable improvements.

Skills

Hardware-aware ML design

HDL (VHDL/SystemVerilog)

ML frameworks (PyTorch/TensorFlow)

Python & C++ tooling

Cross-functional collaboration

Education

MS or PhD in EE/CS/Physics

Tools

HLS tools

hls4ml

FINN

Vitis AI

ML compiler stacks (MLIR/TVM/XLA)

Job description

Fintal Partners in Chicago is seeking researchers and engineers to architect ML models co-designed with traders and software teams, accounting for latency budgets and hardware constraints. You will help shape our custom hardware roadmap and collaborate with hardware engineers from concept to production.

The role blends ML, hardware, and software, requiring understanding of neural networks, quantization, and inference optimization.