ML/AI Timing and Power Flow Expert

191 Altera Corporation; San Jose (CA); On-site; USD 127,400 - 184,400; Full time

Job summary

191 Altera Corporation in San Jose, California is seeking a highly skilled ML/AI Timing and Power Flow Expert. This role focuses on architecting and optimizing advanced ASIC/FPGA implementation flows, driving design efficiency and power convergence.

The ideal candidate holds a Bachelor’s Degree in Electrical Engineering or related fields, with 8+ years of industry experience. Responsibilities include developing robust timing and power flows and leveraging ML/AI methodologies to enhance outcomes.

Salary range for this position is $127,400 – $184,400 USD, with additional incentive opportunities based on performance.

Qualifications

• 8+ years of relevant industry experience in ASIC or FPGA timing/power/library flow development.
• Expertise in STA, power analysis, and library characterization tools.
• Strong coding practices focused on maintainable flow infrastructure.

Responsibilities

• Develop and maintain timing and power flows across the design lifecycle.
• Lead standard-cell and macro library generation.
• Apply ML/AI techniques to improve efficiency and predictability.

Skills

Flow development

Timing analysis

Power analysis

Library generation

Machine learning

Python

Education

Bachelor’s Degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Tcl

Perl

Job description

About Altera

Altera is shaping the future of programmable logic by delivering high‑performance, power‑efficient FPGA solutions that enable innovation across cloud, communications, industrial, automotive, and AI‑driven applications. Our teams push the boundaries of silicon design, verification, and implementation to deliver world‑class products with exceptional quality of results (QoR). We foster a culture of technical excellence, collaboration, and continuous innovation—empowering engineers to solve some of the industry’s most complex challenges while accelerating next‑generation semiconductor technologies.

About the Role

We are seeking a highly skilled ML/AI Timing and Power Flow Expert with deep expertise in flow development, timing, power, library generation, and UPF‑based methodologies, along with strong enthusiasm for applying ML/AI techniques to improve flow efficiency, debug productivity, and overall QoR. In this role, you will architect and optimize advanced ASIC/FPGA implementation flows, focusing on timing and power convergence across full‑chip and block‑level designs. You will leverage machine learning and AI methodologies to enhance predictability, automate bottleneck analysis, and accelerate signoff closure. This is a highly visible, cross‑functional position working closely with design, physical design, CAD, library, and reliability teams to enable best‑in‑class silicon performance and power efficiency.

Key Responsibilities

• Develop, enhance, and maintain robust timing and power flows across the physical design and signoff lifecycle.
• Own and drive STA flows, including timing setup, analysis, and timing collateral generation.
• Design and implement power‑aware flows, including UPF integration, power intent validation, and comprehensive power/timing reporting.
• Lead standard‑cell and macro library generation and characterization flows, including timing, power, noise, and constraint characterization.
• Validation and quality checks for signoff readiness.
• Integration of characterized libraries into STA and power flows.
• Build and maintain scalable, automated flow infrastructure using strong coding and software engineering practices.
• Apply ML/AI‑driven approaches to:
  • Accelerate flow development and turnaround time.
  • Improve debug efficiency for timing, power, library, and convergence issues.
  • Enable smarter analysis, anomaly detection, and trend identification in timing, power, and library data.
  • Generate, analyze, and review timing, power, and library reports, ensuring accuracy, consistency, and signoff quality.
• Collaborate closely with PD, STA, library, power, and methodology teams to continuously improve flows and usability.
• Debug complex timing, power, library, and flow issues across multiple design stages and configurations.

Minimum Qualifications

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 8+ years of relevant industry experience in ASIC or FPGA timing/power/library flow development.
• 6+ years of experience in timing and power flow development and methodology.
• 6+ years of experience with industry‑standard STA, power analysis, and library characterization tools.
• 6+ years of experience with excellent coding practices (Tcl, Python, Perl, or similar), focused on clean, reusable, and maintainable flow infrastructure.
• 6+ years of experience with deep understanding of timing concepts, STA methodologies, timing constraints, and timing collateral generation.
• 6+ years of experience in power analysis, optimization techniques, and comprehensive power reporting methodologies.
• 6+ years of hands‑on experience with library generation and characterization, including timing, power, and noise model development and validation.
• 6+ years of experience working with UPF, including multi‑power‑domain designs and power intent modeling.
• 6+ years of experience in timing collateral generation, library integration into STA/power flows, and complex flow automation coding.
• Demonstrated ML/AI enthusiasm, with interest or experience in applying data‑driven techniques to flow automation, debug, QoR prediction, or trend analysis.

Preferred Qualifications

• 5+ years of experience supporting advanced‑node, large‑scale, complex SoC designs (e.g., multi‑million instance designs across multiple power domains).
• 3+ years of experience working with ML/AI frameworks, data analytics platforms, or statistical methods applied to EDA, timing/power analysis, or library characterization flows.
• 5+ years of experience performing deep data analysis and translating quantitative insights into measurable flow, timing, power, or library methodology improvements.
• 5+ years of demonstrated experience independently driving methodology enhancements end‑to‑end, from problem definition through deployment and production adoption.
• 5+ years of experience collaborating across cross‑functional teams (PD, STA, library, CAD, power) with strong written and verbal technical communication skills.

Salary Range

Salary range (Bay Area, California only): $127,400 – $184,400 USD. We also offer incentive opportunities that reward employees based on individual and company performance.

Employment Details

Job Type: Regular
Shift: Shift1 (United States of America)
Primary Location: San Jose, California, United States

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Recruitment Notice

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.