Mixed-Signal Verification Intern - HDL/UVM

Cirrus Logic; Chandler (AZ); Hybrid; USD 34.000 - 55.000; Vollzeit

Zusammenfassung

Cirrus Logic is seeking highly motivated interns to join our Mixed-Signal Verification Engineering team to support the functional verification of industry-leading mixed-signal products.

This internship offers a unique opportunity to work closely with digital and analog designers, applications engineers, and manufacturing test teams to ensure robust product performance through both pre-silicon verification and post-silicon validation.

Qualifikationen

• Pursuing MS or PhD in Electrical Engineering or related field.
• Strong background in Verilog or VHDL.
• Familiar with SystemVerilog/UVM, Vera, or e.
• Solid understanding of digital design fundamentals and verification methodologies.

Aufgaben

• Assist in verification planning and strategy development.
• Support testbench creation, maintenance, and enhancement.
• Contribute to failure analysis, debug, and resolution efforts.
• Help with coverage analysis and population to ensure thorough verification of mixed-signal products.
• Work on digital/mixed-signal modeling, directed and constraint-random test generation, and verification flow development.

Kenntnisse

Verilog/VHDL

SystemVerilog/UVM

Digital design fundamentals

Ausbildung

MS or PhD in Electrical Engineering

Jobbeschreibung

Cirrus Logic is seeking highly motivated interns to join our Mixed-Signal Verification Engineering team to support the functional verification of industry-leading mixed-signal products.

This internship offers a unique opportunity to work closely with digital and analog designers, applications engineers, and manufacturing test teams to ensure robust product performance through both pre-silicon verification and post-silicon validation.