Mask Design Engineer – Hardware

NVIDIA Corporation; Santa Clara (CA); On-site; USD 108,000 - 184,000; Full time

Job summary

NVIDIA Corporation is seeking a Senior Mask Design Engineer in Santa Clara, CA. The role focuses on designing detailed silicon interposers and collaborating with PTL and I/O/technology teams to meet tight schedules.

You will perform layouts with Cadence and verify against rules, while evaluating trade-offs for size, cost, and system performance. Seniority requires 3+ years in mask/layout design.

Qualifications

• BS in Electrical Engineering or equivalent experience.
• 3+ years proven experience in Mask and Layout Design.
• Proficiency with Cadence layout tools, especially Virtuoso.
• Knowledge of DRC/LVS, and ability to customize decks.

Responsibilities

• Collaborate with PTL and engineers to deliver packaging solutions on tight schedules.
• Perform physical layout for silicon interposer using Cadence tools.
• Study layout floorplans, run verifications, and optimize size and cost.
• Propose trade-offs to PTL and resolve design issues.

Skills

Scripting

Teamwork

Analytical thinking

Education

BS in Electrical Engineering

Tools

Cadence Virtuoso

Calibre

Integrity auto-routing

ICV

Thunder

APD package layout tool

Job description

NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.

What you'll be doing:

• You’ll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
• Performing physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.

What we need to see:

• Hold a B.S. Electrical Engineering or equivalent experience 3+ years proven experience in Mask and Layout Design.
• Deep understanding of layout concepts in submicron CMOS technologies.
• You are an authority with Cadence layout tools - particularly Virtuoso.
• Knowledge of Integrity auto-routing is a plus.
• Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
• Proficient in scripting languages like Perl, Python, Skill, etc.
• Should have knowledge of DRC and LVS checking flows, ability to customize decks.
• Knowledge of APD package layout tool is a plus.
• Good understanding of packaging technology is useful.
• You can work optimally in a team, good interpersonal skills, passion and positive energy.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 108,000 USD - 184,000 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 17, 2026.

This posting is for an existing vacancy.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you #LI-Hybrid

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NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer.

As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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