Low-Power Wireless SoC Engineer – CPU Subsystems

Apple Inc.; Irvine (CA); On-site; USD 123,000 - 214,000; Full time

Job summary

Apple Inc. in Irvine, CA, is seeking a high‑impact ASIC/SoC Design Engineer to design CPU-based subsystems for wireless SoCs.

You will collaborate with SoC architects and IP teams to meet power, performance, and area goals, driving hardware/software partitioning discussions and integrating IPs into the SoCs. The role emphasizes RTL development in SystemVerilog, verification support, and collaboration across design, verification, and platform teams to deliver high-quality silicon for Apple

Qualifications

• Bachelor's degree required.
• Familiarity with the ASIC design flow.
• Knowledge of digital design, SoC architecture, and HDL languages like Verilog.

Responsibilities

• Write micro-architecture and design specifications.
• Code design in SystemVerilog following guidelines, owning RTL development.
• Integrate IP blocks and optimize memories/hard macros.
• Support verification at multiple levels.
• Check design with LINT, CDC, RDC.
• Analyze and optimize area, timing, and power.
• Collaborate across teams to ensure timely, high-quality design delivery.

Skills

Digital design

SoC architecture

Verilog

SystemVerilog

Education

Bachelor's degree

Tools

AXI/AHB bus fabric

UPF

EDA tools

Job description

Apple Inc. in Irvine, CA, is seeking a high‑impact ASIC/SoC Design Engineer to design CPU-based subsystems for wireless SoCs.

You will collaborate with SoC architects and IP teams to meet power, performance, and area goals, driving hardware/software partitioning discussions and integrating IPs into the SoCs. The role emphasizes RTL development in SystemVerilog, verification support, and collaboration across design, verification, and platform teams to deliver high-quality silicon for Apple