Low Power SoC Hardware Architect

Baidu USA; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Baidu USA, located in Sunnyvale, California, is seeking a Low Power SoC Architect to lead the design and enhance efficiency for AI hardware. The ideal candidate will work with innovative teams in both data center and edge SoC environments.

Candidates should possess a strong background in lower power SoC architecture, hold a MS or PhD in Electrical or Computer Engineering, and show proficiency in C/C++ and scripting languages. Excellent communication skills in English and Chinese are essential for success.

Qualifications

• Experience with lower power SoC architecture and design.
• Proficiency in driving efficient low power design features.
• Ability to promote team collaboration and support architecture definition.

Responsibilities

• Design and define lower power subsystems in AI engines.
• Collaborate with engineers and teams to improve power efficiency.
• Drive SoC level power convergence using modeling techniques.

Skills

Lower power SoC architecture

C/C++ proficiency

Power optimization

Communication skills in English and Chinese

Education

MS or PhD in Electrical or Computer Engineering

Tools

Modeling tools

Scripting languages (Perl, Python)

Job description

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world‑class team to explore the fast‑growing AI hardware opportunities and impact on AI industry?

We’re looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.

Description

As a Low Power SoC Architect, you will have the opportunity to independently design and define the lower power subsystem and improve the power efficiency of AI engine, in both data center and edge SoC. You will collaborate with experienced designers, RTL engineers, system and software team, to explore feasibility of ideas, proof of concept and power performance improvement.

Qualifications

• Experience and knowledge of lower power soc architecture and deep expertise in lower power subsystem, power efficient design.
• Lead and drive lower power & most efficient BW to power SoC design, including arch features, RTL changes for low power design, topologies with floorplan/layout and other design aspects
• Work with IPs architects to drive low power design, methodologies, techniques, and features.
• Drive SoC level power convergence by using existing modeling tools and techniques, and developing new state of the art tools, flows, and methodologies.
• Experience and proof of track in power optimization: perf@watt and perf/sq.mm modeling or analysis, is a plus
• Good teamwork with communications and support to solve all levels of architecture definition from micro-architecture to system level to software architecture.
• Proficiency in C/C++ and scripting languages such as Perl or Python.
• Self-driven and leadership skills.
• Knowledge or experience in automotive industry is a plus.
• MS or PhD in Electrical or Computer Engineering.
• Excellent communication skills in both English and Chinese.

Culture Fit

• Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
• Self‑directed: We work best with people that are driven, motivated, and aspire to greatness.
• Hungry to learn: We are eager to see you learn new skills and grow.
• Team orientation: We work in small, fast‑moving teams. We watch out for each other and go after big goals together as a team.

As set forth in Baidu USA’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.