Low-Latency Hardware Engineer (FPGA/ASIC)

wehrtyou; New York (NY); On-site; USD 270,000 - 330,000; Full time

Job summary

Hudson River Trading in New York is seeking hardware engineers to architect and design high-performance compute engines using FPGA and ASIC technologies for low-latency trading decisions.

You will work on on-the-fly transformations of market data and models with complex data structures in RTL, collaborating with FPGA/ASIC teams. Familiarity with SystemVerilog and languages like C++/Python is valued. Competitive base salary and benefits.

Qualifications

• Pursuing a Bachelor's, Masters, or PhD in CS/CE/EE with eligibility for full-time employment in 2027.
• Proficiency in SystemVerilog.
• Deep knowledge of FPGA internals and/or ASIC.
• Excellent digital logic design, optimization, debugging and problem solving.
• Thorough understanding of computer architecture and vendor tool suites.
• Familiarity with C++ and/or Python.
• Comfortable working in a Linux environment.
• Previous internship in digital logic design.
• Expertise in networking protocols, CPU design, physical design, or ML accelerators is a big plus.

Responsibilities

• Contribute to a highly collaborative team, working closely with others to deliver hardware solutions
• Describe and communicate hardware designs at a high level (the interface), low level (step-by-step algorithm/circuit), or anywhere in between
• Analyze and fix problems quickly
• Continuously learn, tinker, and explore new technologies to deepen your hardware expertise
• Challenge your teammates and raise the bar for the work the team produces

Skills

SystemVerilog

FPGA internals

ASIC

Digital logic design

Computer architecture

C++

Python

Linux

Internship in digital logic

Networking protocols

Machine learning accelerators

Education

Bachelor's degree in Computer Science / Computer Engineering / Electrical Engineering

Master's degree or PhD preferred

Eligibility for full-time employment in 2027

Job description

Hudson River Trading in New York is seeking hardware engineers to architect and design high-performance compute engines using FPGA and ASIC technologies for low-latency trading decisions.

You will work on on-the-fly transformations of market data and models with complex data structures in RTL, collaborating with FPGA/ASIC teams. Familiarity with SystemVerilog and languages like C++/Python is valued. Competitive base salary and benefits.