Low-Latency Hardware Design Engineer - ASIC/FPGA

Selby Jennings; Chicago (IL); On-site; USD 90,000 - 140,000; Full time

Benefits offered by this job

Relocation support

Job summary

Selby Jennings is recruiting a Hardware Design Engineer to help build next-generation ASIC/FPGA-based systems in Chicago. You will own architecture, RTL development, verification, and tooling across the design lifecycle.

The role requires 2+ years in relevant hardware roles, strong SystemVerilog/Verilog skills, and familiarity with networking fundamentals. Relocation to Chicago is available for the right candidate.

Qualifications

• Degree in a technical discipline required.
• 2+ years of full-time experience in ASIC/FPGA/RTL or hardware roles.
• Strong RTL and timing fundamentals.
• Experience with Ethernet networking fundamentals is a plus.
• Familiarity with Python or Bash scripting is beneficial.

Responsibilities

• Contribute across architecture, RTL development, verification, and system integration.
• Collaborate with hardware and software engineers to deliver low-latency, high-throughput designs.
• Own portions of the design lifecycle from concept to validation and tooling.

Skills

Python

Bash

Debugging

Collaboration

Multi-clock domains

Networking basics

Education

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related

Tools

SystemVerilog

Verilog

RTL development

Job description

Selby Jennings is recruiting a Hardware Design Engineer to help build next-generation ASIC/FPGA-based systems in Chicago. You will own architecture, RTL development, verification, and tooling across the design lifecycle.

The role requires 2+ years in relevant hardware roles, strong SystemVerilog/Verilog skills, and familiarity with networking fundamentals. Relocation to Chicago is available for the right candidate.