Low-Latency FPGA Engineer for High-Throughput Trading

DRW Holdings, LLC; Chicago (IL); On-site; USD 150,000 - 250,000; Full time

Benefits offered by this job

Medical, dental, vision insurance

401k with discretionary employer match

Discretionary bonus

Life and AD&D insurance

Health Savings Accounts

Job summary

DRW in Chicago is seeking an experienced FPGA engineer to join a trading team. You will build an FPGA application from scratch, participate in full development lifecycle, from system requirements to production, focusing on low-latency, high-throughput designs.

The role requires strong Verilog RTL skills, FPGA design flow knowledge (synthesis, place & route, timing analysis), and the ability to collaborate with software and hardware teams.

Qualifications

• Bachelor’s degree or higher in Computer/Electrical Engineering with 3+ years of FPGA experience
• Solid Hardware Engineering experience, especially with FPGA
• Strong RTL design with Verilog and verification
• Experience in FPGA design flow including synthesis, place & route, static timing analysis
• Experience with SOC architectures, memory & processor subsystems, networking and interconnect

Responsibilities

• Architect and implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up
• Research and evaluate cutting-edge FPGA hardware and technologies
• Propose creative solutions to FPGA/hardware limitations
• Liaise with software and other design teams
• Lab debugging and characterization of new hardware

Skills

Verilog HDL

FPGA design

RTL design

SoC architecture

SystemVerilog

Debugging skills

Project leadership

Hardware co-design

Education

Bachelors or higher in Computer/Electrical Engineering

Tools

Xilinx/Altera FPGA flow

Synthesis

Place & Route

Static timing analysis

Job description

DRW in Chicago is seeking an experienced FPGA engineer to join a trading team. You will build an FPGA application from scratch, participate in full development lifecycle, from system requirements to production, focusing on low-latency, high-throughput designs.

The role requires strong Verilog RTL skills, FPGA design flow knowledge (synthesis, place & route, timing analysis), and the ability to collaborate with software and hardware teams.