Lead Test Architect — Analog & Mixed-Signal Solutions

Renesas Electronics; San Jose (CA); On-site; USD 191,000 - 238,000; Full time

Job summary

Renesas Electronics is seeking a Principal Test Engineer to lead the Test Architecture in our Analog and Mixed-Signal division. You will define test methodology, collaborate with design and product teams, and drive architecture for high-volume semiconductor testing.

The role emphasizes leadership in ATE development, mixed-signal test solutions, and optimization of testers across wafer sort and final test. This is a full-time, on-site position in San Jose, with a competitive compensation package.

Qualifications

• BS or MS in Electrical Engineering, Physics, or related field with 10+ years in semiconductor test engineering.
• Extensive Automatic Test Equipment (ATE) development experience on major platforms.
• Experience designing test hardware and software for mixed-signal test solutions.
• Experience with new product introduction from samples to production test systems.
• Familiarity with analog/mixed-signal devices and related test concepts.

Responsibilities

• Define and drive test architecture, methodology, and innovation for analog and mixed-signal products.
• Collaborate with IC design, product engineering, and test teams to establish DFT requirements.
• Architect and optimize mixed-signal test hardware and software to improve quality and throughput.
• Evaluate tester roadmaps and drive process improvements across the org.
• Provide technical leadership and mentorship on test strategies and problem-solving.

Skills

ATE development

Test hardware design

Test software development

Mixed-signal expertise

Electrical engineering principles

Education

Bachelors/Masters in Electrical Engineering

Tools

Advantest 93K

ETS

Teradyne FLEX

Diamondx

LTX

SPEA

Job description

Renesas Electronics is seeking a Principal Test Engineer to lead the Test Architecture in our Analog and Mixed-Signal division. You will define test methodology, collaborate with design and product teams, and drive architecture for high-volume semiconductor testing.

The role emphasizes leadership in ATE development, mixed-signal test solutions, and optimization of testers across wafer sort and final test. This is a full-time, on-site position in San Jose, with a competitive compensation package.