Lead SoC Clock & Power Validation for AI/HPC

Qualcomm; Austin (TX); Presencial; USD 146 000 - 218 000; Tempo integral

Resumo da oferta

Qualcomm Technologies, Inc. in Austin, TX seeks an experienced engineer to lead end-to-end validation of clock, power, reset, and PMIC integration for next-gen AI accelerator platforms.

You will drive pre- and post-silicon validation of Clocking infrastructure, DVFS, and low-power features. Collaborate with Architecture, Design, Verification & Firmware to debug root causes and deliver production-quality silicon across program milestones.

Qualificações

• Bachelor's degree in engineering or related field.
• 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Exposure to clock/power validation and lab instrumentation (multimeter, oscilloscopes, logic analyzer).
• Proficient in C, Python.
• Experience with debug tools and ARM-based SoCs.

Responsabilidades

• Own the E2E bare metal framework validation SoC clock and power architectures.
• Validation planning – understand design changes and test requirements.
• Test plan development – document test strategy and dependencies.
• Conduct validation strategy and test plan reviews with stakeholders.
• Develop scalable device drivers and system tests using C.
• Debug complex issues on pre-Si and post-Si platforms and provide direction.
• Review validation platform schematics for post-Si debug support.
• Automate validation processes using Python, Perl, and shell.
• Operate lab instruments and collaborate across time zones.

Conhecimentos

Clocking validation

Power management

C programming

Python scripting

Lab instruments

Debug tools

ARM debugging

Formação académica

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Ferramentas

Verilog/SystemVerilog

JTAG debugging tools

Descrição da oferta de emprego

Qualcomm Technologies, Inc. in Austin, TX seeks an experienced engineer to lead end-to-end validation of clock, power, reset, and PMIC integration for next-gen AI accelerator platforms.

You will drive pre- and post-silicon validation of Clocking infrastructure, DVFS, and low-power features. Collaborate with Architecture, Design, Verification & Firmware to debug root causes and deliver production-quality silicon across program milestones.