Lead Product Engineer

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 119,000 - 221,000; Full time

Benefits offered by this job

Paid vacation and holidays

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plans

Bonus and equity

Job summary

Cadence Design Systems, Inc. is seeking a High-performance and Power-Critical CPU/GPU Implementation and Methodology Engineer in California.

You will own full-chip and block-level implementation from RTL to Signoff, including floorplanning, placement, routing, timing closure, and power integrity analysis. Responsibilities include developing automation scripts, optimizing PPA, and collaborating with cross-functional teams.

Qualifications

• Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
• Strong understanding of physical design fundamentals: floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, electromigration.
• Experience with timing closure methodologies for setup, hold, power, and area optimization.
• Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
• Need to be automation savvy and able to develop scripts and methodologies to improve productivity and design quality.
• Exposure to machine learning and AI-assisted optimization techniques is a plus.

Responsibilities

• Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
• Collaborate with architecture, RTL, verification, methodology, and CAD teams to ensure design quality and convergence.
• Develop scripts and tools to improve design productivity and PPA outcomes.
• Evaluate and apply industry-standard implementation and signoff tools.
• Address challenges related to advanced nodes (5nm and below) such as congestion and variability.

Skills

RTL to Signoff

Place-and-route

Timing closure

Power analysis

UPF/CPF

Power gating

Multi-voltage

Clock gating

Python

Tcl

Perl

Shell

Machine learning

AI optimization

Signoff tools

PPA optimization

Tools

Python

Tcl

Perl

Shell

Job description

SAN JOSE

Full time

R56957

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

High-performance and Power-Critical CPU and/or GPU Implementation and Methodology Engineer

Responsibilities / Skills

Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.

• Strong understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.

• Experience with timing closure methodologies for setup, hold, power, and area optimization.

• Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.

• Need to be automation savvy and able to develop scripts, utilities, and methodologies to improve productivity and design quality.

• Prior experience in Python, Tcl, Perl, Shell, or other programming/scripting languages is a plus.

• Exposure to machine learning and AI-assisted optimization techniques is a plus.

• Familiarity with industry-standard implementation and signoff tools

• Understanding of advanced technology nodes (5nm and below) and associated challenges including congestion, variability, power integrity, and manufacturability is desirable.

• Strong debugging and problem-solving skills with the ability to analyze complex design issues and drive them to resolution.

• Good communication skills and ability to work effectively with cross-functional teams including architecture, RTL, verification, methodology, and CAD teams.

• Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity is highly desirable.

• Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation is a plus.

The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.