Lead Process Engineer - Backside Processing, CMP & Thermal

NOKIA

Sunnyvale (CA)

On-site

USD 140,000 - 190,000

Full time

4 days ago

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Job summary

Nokia Optical Networks seeks an experienced Staff Process Engineer to lead backside processing, thinning, CMP, and thermal processing for InP photonic IC manufacturing. You will own thinning technologies, CMP planarization, and thermal recipes while collaborating with multiple engineering teams to deliver robust, manufacturable solutions.

The role demands strong ownership, 24x7 production support, and the use of DOE/SPC/data analytics to optimize process capability and yield.

Qualifications

MS or PhD in Materials Science, Mechanical, Electrical, Chemical, Physics, or related field.
BS with 5+ years in semiconductor/photonic manufacturing also considered.
Strong experience in wafer thinning, backside processing, CMP, thermal processing.
Experience with semiconductor process development, integration, yield improvement, and production support.
Working knowledge of polishing systems, grinding equipment, furnace systems, RTP tools, process control methodologies, and materials characterization techniques.
Demonstrated experience using DOE, SPC, JMP, statistical analysis, and data‑driven problem solving.
Strong ownership mindset with demonstrated ability to drive projects independently and deliver measurable business impact.
Excellent troubleshooting and cross‑functional collaboration skills.

Responsibilities

Develop, qualify, and sustain backside wafer processing, wafer thinning, lapping, grinding, CMP, and thermal processes for InP photonic IC manufacturing.
Own and optimize wafer thinning technologies including mechanical grinding, lapping, polishing, stress relief, and final substrate thickness control.
Develop and optimize CMP processes for planarization, surface finish improvement, thickness control, defect reduction, and yield enhancement.
Own thermal processes including annealing, alloy formation, furnace processing, RTP, bake, and temperature‑sensitive material integration.
Optimize metrics including wafer thickness uniformity, TTV, surface roughness, planarity, bow/warp, defectivity, thermal stability, and device performance.
Drive defect reduction, yield improvement, and process capability using DOE, SPC, advanced analytics, and statistical process control.
Perform root‑cause analysis and implement corrective actions for process excursions, wafer breakage, polishing defects, thermal non‑uniformity, equipment failures, and integration challenges.
Analyze processes from a first‑principles physics‑based approach to understand wafer mechanics, polishing, thermal interactions, and material behavior.
Collaborate with lithography, wet/dry etch, thin film, metallization, reliability, and device engineering teams to optimize process integration.
Lead evaluations of new consumables, slurries, pads, grinding wheels, thermal recipes, and process technologies.
Partner with equipment vendors and materials suppliers on hardware improvements, process optimization, reliability enhancements, and cost‑of‑ownership initiatives.
Support technology transfer from development to manufacturing while maintaining process stability and manufacturability.
Provide rapid response and leadership during process excursions and production events.
Support 24x7 manufacturing environment through escalation, troubleshooting, and on‑call support.
Utilize AI‑enabled engineering tools, automation, and data analytics to improve development efficiency and manufacturing performance.