Lead Physical Design Engineer

Fractile; Bristol (VA); On-site; USD 120,000 - 180,000; Full time

Job summary

Fractile, located in Bristol, is looking for a Lead Physical Design Engineer to oversee complex IC physical designs. The ideal candidate will bring over 10 years of advanced technology experience, expertise in EDA tools, and a proven ability to mentor and lead teams. This role emphasizes collaboration across departments to ensure optimal chip functionality while driving innovative projects in AI technology. Join us to shape the future of AI and revolutionize the industry!

Qualifications

• 10+ years of experience in physical design for advanced technology nodes.
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.

Responsibilities

• Drive the physical implementation of ASIC/SoC designs.
• Lead or contribute to full-chip execution and chip leadership.
• Collaborate with cross-functional teams on performance optimisation.

Skills

EDA tools expertise

Timing closure

Problem-solving skills

Teamwork

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys Fusion Compiler

Mentor Graphics Calibre

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Lead Physical Design Engineer to contribute to our next-generation chip designs. As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. In this role, you will take on leadership responsibilities across multiple dimensions, including full-chip ownership, leading a team of physical design engineers, and contributing to broader chip-level physical design leadership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Own power planning and analysis, addressing IR drop, electromigration, and related effects.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
• Mentor junior engineers and contribute to building strong physical design practices across the team.
• Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Proven ability to take ownership of complex designs and drive them to completion.
• Experience mentoring engineers and leading physical design efforts.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 90+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.