Semiconductor Test Engineering Team Leader

Fractile; Bristol (VA); On-site; USD 122,000 - 162,000; Full time

Job summary

A pioneering technology firm in Bristol is seeking a Semiconductor Test Engineering Team Leader. This role involves managing test engineering activities for an advanced AI accelerator chip program, including strategy development, team leadership, and vendor oversight. Candidates should possess a relevant degree and over 8 years of semiconductor test engineering experience. The firm promotes a collaborative culture focused on innovation and has rapidly expanded since its founding in 2022.

Qualifications

• Minimum 8 years in semiconductor test engineering, including leadership roles.
• Deep experience with ATE test development.
• Strong understanding of memory testing and high-speed interface testing.
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high‑speed interface testing.
• Experience managing external test development partners or OSATs.
• Proven ability to lead and mentor test engineering teams.
• Solid background in advanced CMOS nodes and familiarity with advanced packaging test challenges.
• Expertise in silicon debug, characterization, and correlation across ATE and system‑level environments.
• Ability to collaborate across design, architecture, product engineering, packaging, and operations.

Responsibilities

• Drive the manufacturing test strategy for an AI accelerator chip.
• Manage a team of chip test engineers.
• Oversee test development for high-speed interfaces.
• Define and drive test software architecture, DFT usage, and test pattern development strategies for high‑speed logic, SRAM, DRAM, and High Speed IO blocks.
• Work closely with design, DFT, product engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success.
• Oversee test development for high speed interfaces such as PCIe Gen6 and multi‑Ghz LPDDR.
• Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system‑level tests).
• Lead silicon bring‑up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities.
• Define KPIs and metrics for subcontractor performance, test coverage, yield, time‑to‑test, and cost optimization.
• Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure.
• Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die‑to‑die IO testing).
• Support qualification, reliability testing, and high‑volume manufacturing transfer.

Skills

Semiconductor test engineering

Leadership

DFT (scan, ATPG, LBIST, MBIST)

Silicon debug

Leadership / mentoring

CMOS nodes / packaging test challenges

Silicon debug & characterization

Cross-functional collaboration

Education

BS/MS/PhD in Electronics and Electrical Engineering or related field

Tools

Advantest 93K

Teradyne

Job description

Semiconductor Test Engineering Team Leader

Bristol

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

We are looking for a team leader for Semiconductor IC test engineering activities for an advanced AI accelerator chip program, including ownership of subcontracted test development, internal team leadership, and delivery of high-quality, high-volume-capable test solutions. The role spans test strategy, test architecture, vendor oversight, team management, and hands‑on technical guidance across digital, memory, and high‑speed interface domains.

Key Responsibilities

• Drive the manufacturing test strategy for an AI accelerator chip featuring PCIe Gen6, LPDDR, advanced CMOS nodes, and advanced packaging (e.g., 2.5D/3D, chiplet).
• and manage a team of chip test engineers responsible for test planning, test program development, pattern bring‑up, silicon characterization, debug, and optimization.
• Manage subcontracted test development partners (OSATs, ATE vendors, external engineering services). Includes scoping, technical oversight, schedule tracking, and quality control of deliverables.
• Define and drive test software architecture, DFT usage, and test pattern development strategies for high‑speed logic, SRAM, DRAM, and High Speed IO blocks.
• Work closely with design, DFT, product engineering, packaging, and validation teams to ensure robust test coverage, manufacturability, and yield ramp success.
• Oversee test development for high speed interfaces such as PCIe Gen6 and multi‑Ghz LPDDR.
• Guide development of structural and functional test content (scan, MBIST, JTAG, HSIO tests, system‑level tests).
• Lead silicon bring‑up and development on ATE: correlation, failure analysis, shmooing, corner testing, stress testing, and yield improvement activities.
• Define KPIs and metrics for subcontractor performance, test coverage, yield, time‑to‑test, and cost optimization.
• Drive continuous improvement in test methodologies, automation, data analytics, and debug infrastructure.
• Ensure robust test flows for advanced packaging (thermals, interposer/bridge connections, TSV integrity, die‑to‑die IO testing).
• Support qualification, reliability testing, and high‑volume manufacturing transfer.

Required Qualifications

• BS/MS/PhD in Electronics and Electrical Engineering or related field.
• 8+ years in semiconductor test engineering, including leadership or technical lead roles.
• Deep experience with ATE test development (e.g., Advantest 93K, Teradyne).
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high‑speed interface testing.
• Experience managing external test development partners or OSATs.
• Proven ability to lead and mentor test engineering teams.
• Solid background in advanced CMOS nodes and familiarity with advanced packaging test challenges.
• Expertise in silicon debug, characterization, and correlation across ATE and system‑level environments.
• Ability to collaborate across design, architecture, product engineering, packaging, and operations.

Preferred Qualifications

• Experience with AI/ML accelerator chips or other high‑performance compute ICs.
• Prior involvement with PCIe Gen5/Gen6 or LPDDR4/5/6 test methodologies.
• Familiarity with signal‑integrity‑aware test development and high‑speed IO margining.
• Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full‑stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 70+, which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem‑solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.