DFT Engineer

Fractile; Bristol (VA); On-site; USD 80,000 - 120,000; Full time

Job summary

Fractile in Bristol, VA seeks a candidate for the DFT role in a multi-core AI accelerator ASIC. Responsibilities include contributing to the DFT architecture, integrating DFT tools into the EDA workflow, and automating DFT processes. Candidates should have a degree in Electrical or Computer Engineering, understanding of DFT and digital design. Scripting skills and familiarity with EDA tools are essential. The company values ownership, rapid iteration, and teamwork in a collaborative environment.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, or similar.
• Experience in DFT, digital design, or related ASIC development.
• Good understanding of scan, ATPG, memory BIST and digital test concepts.
• Familiarity with mainstream EDA tools.
• Scripting skills (Python, Tcl, or similar).

Responsibilities

• Contribute to the DFT architecture of a multi-core AI accelerator SoC.
• Drive integration of DFT tools into the EDA flow.
• Implement scan insertion, compression, and test logic.
• Generate and analyze ATPG patterns for structural faults.
• Support MBIST implementation for embedded memories.

Skills

DFT architecture

Scan insertion

ATPG patterns

Memory BIST

Scripting skills (Python, Tcl)

Education

Degree in Electrical Engineering or Computer Engineering

Tools

Mainstream EDA tools

Job description

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

Join the team implementing DFT for a large, multi-core AI accelerator ASIC. You will work on scan, ATPG, and memory test, contributing to a robust and scalable test solution while developing your expertise in advanced SoC design.

Key Responsibilities

• Contribute to the DFT architecture of a multi-core AI accelerator SoC
• Drive integration of DFT tools into the EDA flow
• Implement scan insertion, compression, and test logic
• Generate and analyze ATPG patterns for structural faults
• Support MBIST implementation for embedded memories
• Work with physical design to ensure clean scan chain implementation and timing closure
• Develop scripts and automation to improve DFT workflows
• Support silicon bring-up, debug, and test analysis
• Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp

Required Experience

• Degree in Electrical Engineering, Computer Engineering, or similar
• Experience in DFT, digital design, or related ASIC development
• Good understanding of scan, ATPG, memory BIST and digital test concepts
• Familiarity with mainstream EDA tools
• Scripting skills (Python, Tcl, or similar)

Profile

• Eager to learn and grow in DFT and large-scale ASIC design
• Detail-oriented and comfortable working with complex systems
• Collaborative and responsive in a fast-moving team

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is

About us

• Founded in 2022, team of 80+ which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.