Lead III-V Photonics Designer for Silicon Integration

Salience Labs Ltd

San Francisco (CA)

On-site

USD 150,000 - 190,000

Full time

5 days ago

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Job summary

Salience Labs Ltd in the UK seeks a senior photonics/III-V device engineer to lead the development of active devices for silicon photonics integration. You will take devices from epitaxial stack through fabrication with external partners to characterization and qualification.

The role demands strong hands-on experience with III-V epitaxy, device design and test, plus leadership to mentor engineers and grow the team.

Qualifications

PhD in physics, photonics, electrical engineering or related field with 6+ years of relevant experience, or a Master's with 8+ years, including 4+ years in III-V devices.
Proven track record taking III-V devices from concept through design, fabrication and test.
Deep understanding of semiconductor laser and amplifier physics: optical gain, carrier dynamics, quantum-well design, noise, gain saturation and nonlinearities.
Hands-on knowledge of III-V epitaxy and fabrication processes (e.g. MOCVD/MBE growth, lithography, etching, passivation, metallisation, facet/AR coating), and experience working with external foundries.
Experience characterising amplifiers or lasers, including optical spectrum analysis, gain and noise measurement, wafer-level probing, temperature-controlled testing and test automation.
Experience with simulation and layout tools for photonic devices, such as Lumerical, Photon Design, Crosslight, RSoft, COMSOL, KLayout, L-Edit or Cadence Virtuoso.
Proven ability to lead technical projects across design, process, test and packaging functions, and experience mentoring or supervising engineers.
Excellent communication skills, critical thinking, attention to detail and self-motivation.

Responsibilities

Lead design and modelling of III-V active devices, including epitaxial layer structure, gain and power modelling, optical mode design, and electrical and thermal design.
Own the technology roadmap and device specifications for your area, translating system requirements into device design and integration targets.
Lead mask design and tape-outs, including GDS layouts, test structures and design-of-experiment splits.
Manage fabrication runs with external epitaxy and foundry partners: define process flows, review process and in-line data, and resolve yield issues as the technology scales.
Define and lead the characterisation strategy at wafer, chip and integrated-PIC level, including building and automating test setups.
Analyse test data, correlate measured performance with design and process variations, and drive design iterations to close performance gaps.
Work with packaging and reliability engineers on burn-in, accelerated ageing, failure analysis and qualification.
Mentor engineers and, as the team grows, help recruit and develop new team members.