Lead, Compiler & Runtime Engineering for AI Accelerators

Normalcomputing; Mountain View (CA); On-site; USD 230,000 - 340,000; Full time

Job summary

Normal Computing is seeking an Engineering Manager, Compiler & Runtime to build and lead the team that writes the core software for translating PyTorch models to our memory-centric hardware. You will hire and mentor engineers, set the product roadmap, and partner with the senior compiler architect to align software with hardware goals.

The role focuses on running the compiler, runtime, and kernels end-to-end, with work on simulators, FPGA prototypes, and eventual silicon, ensuring a smooth

Qualifications

• Experience leading engineers building compilers, runtimes, or kernels for accelerators.
• Proven track record hiring and mentoring systems engineers.
• Hands-on familiarity with ML compiler stacks and PyTorch workflows.
• Experience delivering software on hardware schedules from simulation to bring-up.
• Ability to collaborate with hardware teams and review design trade-offs.

Responsibilities

• Build and lead the compiler & runtime team and align with hardware roadmap.
• Hire engineers, plan work, and deliver milestones.
• Review designs with the compiler architect and trade-offs.
• Coordinate with hardware drivers/firmware and with serving and simulation work.
• Maintain compatibility with simulators, FPGA prototypes, and silicon as development progresses.
• Establish testing, release, and code-review practices.

Skills

Team leadership

Compiler & runtime

Hardware-software co-design

Hiring & mentoring

PyTorch/ML workflows

Tools

FPGA

Simulators

Job description

Normal Computing is seeking an Engineering Manager, Compiler & Runtime to build and lead the team that writes the core software for translating PyTorch models to our memory-centric hardware. You will hire and mentor engineers, set the product roadmap, and partner with the senior compiler architect to align software with hardware goals.

The role focuses on running the compiler, runtime, and kernels end-to-end, with work on simulators, FPGA prototypes, and eventual silicon, ensuring a smooth