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Cadence seeks an engineer to contribute to the Palladium emulation platform and its compiler development. You will apply multi-threading and distributed computing to handle large-scale compile problems and optimize logic, partitioning and scheduling for high performance.
Strong knowledge of data structures, algorithms, and C/C++ is required, with Linux/Unix development exposure. Verilog/SystemVerilog experience is a plus, and MS/PhD candidates are encouraged to apply.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Cadence Palladium Platform is world most scalable emulation system that verifies most of the latest design innovations in electronics worldwide. We are looking for a talented engineer to join our team and contribute to the world’s fastest emulator compiler development. You’ll have a great opportunity to make a difference by applying your creativity and problem-solving skills, learn and/or apply multi-threading/distributed computing to solve large scale compile problems such logic optimization, partitioning and scheduling.
Strong understanding of software data structure and algorithms and proficiency in C/C++ are basic job requirements.
The annual salary range for Massachusetts is $101,500 to $188,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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